Fix JIT bug related to immediate doubles

Change 256211 (JIT: Performance Fix for const doubles) introduced a
defect that can cause the JIT to use the wrong floating point
double constant in traces in which the following conditions hold:

   o Two (or more) different 64-bit floating point constants are used.
   o The physical register holding the first constant is still live
     at the time the second constant is used.
   o The low 32 bits of the two constants are identical.

In this situation, the load/copy optimization pass will incorrectly
determine that the two constants are the same, delete the load of
the second constant and re-use the first constant value.

Note: this problem only occurs with 64-bit floating point literals.
64-bit long literals are unaffected.

This CL works around the problem, and a subsequent CL will rework
disambiguation of 64-bit immediates in a somewhat cleaner fashion.

(cherry-pick of c1757a6deab0ca0bfd42c38612d92b2f26c41dbe.)

Change-Id: I795b4b753550d2745cbbdd83ae25f4a7088990f6
Fix JIT initialization race

See b/8767735 Slow thread in thread spin test

A race exists in thread creation/JIT initialization that can
leave the JIT permanantly disabled for a thread (typically
the first interpreter thread).

(cherry-pick of 67985d960f5c877f86d0bba251d2d55c7a062b8d.)

Change-Id: Ic7e3a1cde2833ac78455fa5d465156b5e0896fc1
Fix some leaks in VfyBasicBlock & BitVector.

Change-Id: I20050135588fc96268911b8ab690b04c8ad949bc
Fix a minor bug in dvmCreateInterpThread

Change-Id: I452ee02290bc7e0be7fefcf5755c5cd9628142dc
Fix minor leaks caused by failed initialization in JNI_CreateJavaVM

Change-Id: I97e4b162fa729c97a1e71786b696f2befed56835
Fix a minor leak in dvmCreateInlineSubsTable

Change-Id: I1dce0e24c861903e8f5eccb23a7e2865ae8c9cec
JIT: Combine add with shift and offset for array load & store.

Optimize long and double array load / store for ARM JIT.
Array load / store performs a logical shift left and add,
replace it with add capable of performing shift in the
same instruction.
Array load / store performs an add instead of using offset
for vldr/vstr. Replace the add and vldr/vstr with a vldr/vstr
that is capable of handling offset.

This improves performance for usecases involving long and double
array code execution in Dalvik. E.g WindowOrientation.

Change-Id: I90220c349ab936cdba1987139ccdf4dc31d7bbb0
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Combine shift & sub for monitor unlock.

Optimize monitor unlock for ARM Thumb2 JIT.
Monitor unlock performs a logical shift left
and sub, replace it with a sub capable of
performing the shift in the same instruction.

This improves performance for usecases involving code
executing in Dalvik.

Change-Id: Iaf062d750c3bc941926f3c3b8a64dc9c7984a477
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Use vmla.f64 instead of vmuld + vaddd.

Optimize Java double floating-point performance for ARM JIT.
Whenever a double mul is followed with a double add,
replace it with a combined mul and add instruction.

This improves double arithmetic performance for code executing
in Dalvik.

Change-Id: Ia4fccf4fa53aa9fb4a76cbf388f5ea16dcef32b7
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Allow use of cbz/cbnz for conditional branch gen.

Optimize conditional branch generation when comparing
with zero for ARM JIT. When possible use cbz/cbnz
instead of cmp+beq/cmp+bne.

This improves performance for usecases involving
code execution in Dalvik.

Change-Id: I8f7c44c87eb73d4da00a48fd86220a62cb0515f5
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Use rsb and shift in easy multiply.

For easy multiplication using reverse subtract (when
lit is 2^n-1) use the barrel shifter for rsb.

This improves arithmetic performance for code executing
in Dalvik. E.g String.hashCode.

Change-Id: Ifb086dcec344b30fd3e392ac21d508b43e820cdc
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>

Conflicts:
	vm/compiler/codegen/arm/ArmLIR.h
	vm/compiler/codegen/arm/Assemble.cpp
	vm/compiler/codegen/arm/Thumb/Gen.cpp
	vm/compiler/codegen/arm/Thumb2/Gen.cpp
JIT: Combine add with shift.

Optimize logical shift for ARM JIT.
Whenever logical shift is followed by an add,
replace it with an add capable of performing
the shift in the same instruction.

This improves performance for usecases
involving code executing in Dalvik.

Change-Id: I3cb807b6d6ef4b053a19e2703676a93a930eb963
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>

Conflicts:
	vm/compiler/codegen/Optimizer.h
	vm/compiler/codegen/arm/LocalOptimizations.cpp
JIT: Suppress loop suspend checks.

Suppresses the suspend checks generated by the JIT compiler,
for small loops. This improves performance and code size of loops.

Change-Id: I5df70422668eb53c7789899823586daeee265633
Signed-off-by: Henrik Smiding <henrik.smiding@stericsson.com>
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
JIT: Hoist loop load operations above loop.

Hoists Dalvik frame load operations outside of loops, when possible.
This improves performance in most loops, and is noticable in many
applications.

Change-Id: Ibe42b509b50a13f19758fd923f31d703e33a51c6
Signed-off-by: Henrik Smiding <henrik.smiding@stericsson.com>
Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>

Conflicts:
	vm/compiler/Loop.h