doc: Starts moving user manual to texinfo.
all: Re-organise folder structure.

Add synthesis makefile and release script.
Remove xilinx/ folder (not used any more).
Rename cpld project and sources folder.
Move fpga related stuff to the hdl/ folder.
all: Rename src/ folder in rtl/.
struct: Rename rtl/ folder in src/
hdl: Update manifest and ise project with new folder structure.
hdl: Use STROBE only for parallel data input and sample/store data on CLOCK in all modes.
hdl: Sync data inputs to sys clock (parallel and cvorb modes).
     Positive input polarity by default, polarity now selectable by csr reg.
     Module disabled by default.
     Module must be disabled to change mode (protected in gateware).
     When no sampling clock, frequency meter shows 0.
hdl: Add new mode, rtm parallel with bit 31 used as strobe.

This mode is specific for CPS RF Frev measurment.
doc: Work on user manual.
hdl: Add new mode, rtm parallel with bit 31 used as strobe.

This mode is specific for CPS RF Frev measurment.
doc: Final version of the doc for comments.
doc: Update test procedure notes.
doc: Add figures sources, update makefile and script, add gitignore.
doc: Move front panel image extraction to the makefile.
     Remove cern logo pdf (is generated from svg by make).
doc: Apply Erik's comments.
hdl: Update script with official gateware release location.
hdl: Fix some comments.
hdl: Release v2.00