drm/edid: add quirk for Medion MD30217PG

This LCD monitor (1280x1024 native) has a completely
bogus detailed timing (640x350@70hz).  User reports that
1280x1024@60 has waves so prefer 1280x1024@75.

Manufacturer: MED  Model: 7b8  Serial#: 99188
Year: 2005  Week: 5
EDID Version: 1.3
Analog Display Input,  Input Voltage Level: 0.700/0.700 V
Sync:  Separate
Max Image Size [cm]: horiz.: 34  vert.: 27
Gamma: 2.50
DPMS capabilities: Off; RGB/Color Display
First detailed timing is preferred mode
redX: 0.645 redY: 0.348   greenX: 0.280 greenY: 0.605
blueX: 0.142 blueY: 0.071   whiteX: 0.313 whiteY: 0.329
Supported established timings:
720x400@70Hz
640x480@60Hz
640x480@72Hz
640x480@75Hz
800x600@56Hz
800x600@60Hz
800x600@72Hz
800x600@75Hz
1024x768@60Hz
1024x768@70Hz
1024x768@75Hz
1280x1024@75Hz
Manufacturer's mask: 0
Supported standard timings:
Supported detailed timing:
clock: 25.2 MHz   Image Size:  337 x 270 mm
h_active: 640  h_sync: 688  h_sync_end 784 h_blank_end 800 h_border: 0
v_active: 350  v_sync: 350  v_sync_end 352 v_blanking: 449 v_border: 0
Monitor name: MD30217PG
Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz
Serial No: 501099188
EDID (in hex):
          00ffffffffffff0034a4b80774830100
          050f010368221b962a0c55a559479b24
          125054afcf00310a0101010101018180
          000000000000d60980a0205e63103060
          0200510e1100001e000000fc004d4433
          3032313750470a202020000000fd0038
          4c1e530e000a202020202020000000ff
          003530313039393138380a2020200078

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reported-by: friedrich@mailstation.de
Cc: stable@vger.kernel.org
drm/radeon: switch r6xx+ to using CP DMA for the blit copy callback

CP DMA is lighter weight than using the 3D engine.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/kms: remove r6xx+ blit copy routines

No longer used now that we use the async dma engines or
CP DMA for bo copies.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add UVD->DPM helper function (v5)

Add a helper function for counting the number of open stream handles.

v2: fix copy-pasta in comments and whitespace error
v3: make function static since it's only used in radeon_uvd.c
at the moment
v4: make non-static again for future changes
v5: make static again for new rework of dpm uvd changes

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/dpm: use multiple UVD power states (v3)

Use the UVD handle information to determine which
which power states to select when using UVD.  For
example, decoding a single SD stream requires much
lower clocks than multiple HD streams.

v2: switch to a cleaner dpm/uvd interface
v3: change the uvd power state while streams
are active if need be

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/dpm: rework thermal state handling

1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: default to 1024M gart size on rv770+

Newer asics have a lot of vram so it's less of an
issue to waste a little more space for the gart
page table.  This gives us some additional gart space
before having to migrate to non-gart system ram
for games, etc. where we use up most of vram.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/dpm: use performance state if no UVD state

Newer asics don't have specific UVD states.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/kms: fix up dce8 display watermark calc for dpm

Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/cik: implement some more atom helpers for DPM

Required for DPM on CIK.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: switch CIK to use radeon_ucode.h

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/cik: add support for pcie gen1/2/3 switching

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add support for ASPM on CIK asics

Enables PCIE ASPM (Active State Power Management) on
CIK asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/cik: restructure rlc setup

Restructure rlc setup to handle clock and power
gating.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: clean up sumo_rlc_init() for code sharing

This will eventually be shared with newer asics to
reduce code duplication.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: convert SI,CIK to use sumo_rlc functions

and remove duplicate si_rlc functions.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: implement clock and power gating for CIK (v3)

Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: add indirect accessors for dift registers on CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/sumo add helper to go from vid7 to vid2

Needed for DPM on KB/KV.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: switch to pptable.h

Internally we switched to using a separate header for
atombios pplib definitions.  Switch over the open source
driver.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>