cores: adv_debug_sys: For X to zero during sim in crc module

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_intercon: assert wbm_err_o on non-match accesses

Instead of falling back to the first slave when no match occur,
signal a wishbone error. If fallback behaviour is desired,
it's still acheivable by extending the range of the slave
to which the fallback is desired.
avalon_to_wb_bridge: abort read on wbm_err_i
cores: add vga_lcd core

This adds the vga_cld core from opencores, with two accompanying
patches.
One for a typo of a signal and one for fifo auto resync.
Merge pull request #12 from fjullien/for-upstream-new

cores: adv_debug_sys: Force X to zero during sim in crc module
Merge pull request #13 from skristiansson/for-openrisc

cores: updates fixes and additions
wb_avalon_bridge: wb burst to avalon pipeline access translation

Since there is no way of knowing what kind of (avalon) bursts
are suppported by the slaves we connect to, the wishbone bursts
are translated into avalon pipelined reads rather than avalon
bursts.
Wishbone allows for bursts to be ended at arbitrary cycles
(with the 'end burst' commmand), such cases are handled by
waiting out the remaining pending reads and filtering out the
readdatavalid signal from the wb_ack signal.
cores: uart16550: fix wb slave behavior

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems: add Altera de1 board support

This is a minimal port. VGA, SD-CARD and PS2 will come later.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'for-upstream-new' of https://github.com/fjullien/orpsoc-cores
Merge branch 'for-openrisc' of https://github.com/skristiansson/orpsoc-cores
Merge branch 'for-openrisc-de1' of https://github.com/fjullien/orpsoc-cores
Merge branch 'master' of github.com:openrisc/orpsoc-cores
systems/de0_nano: fix .system syntax

Remove simulation related options

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems/de1: fix .core and .system syntax

de1.core:

- remove leading spaces from simulator options
- add modelsim to the list of supported simulator

de1.system:

- Remove simulator related options

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
de0_nano: remove non-existing altera_virtual_jtag.v from src_files
de0_nano: connect mor1kx reset to debug_if reset output

Makes it possible to reset the cpu via a jtag interface.

For future improvements - The debug_if should be able to reset the whole
system (excluding itself).
sockit: add possibility to clock fpga ddr3 seperately

but we still clock it with the wb clock for now
cores: add opencores ac97 controller core
cores: add opencores i2c master controller core