test checkin
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.

* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb)  field coding types
and use it to encode register pair numbers when required.

* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.

* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.

* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
	PR gas/15082
	* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
	from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
	tic6x_operand_xregpair operand coding type.
	Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
	opcode field, usu ORXREGD1324 for the src2 operand and remove the
	TIC6X_FLAG_NO_CROSS.

	* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
	cross-path.
	* gas/tic6x/insns-bad-1.l: Update expected output.
	* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
	cross-path.
	* gas/tic6x/insns-c674x.d: Update expected output.
	* elf32-h8300 (h8_relax_section): Add new relaxation of mov
	@(disp:32,ERx) to mov @(disp:16,ERx).
	(R_H8_DISP32A16): New reloc.
	Comments added and corrected.
	* reloc.c (BFD_RELOC_H8_DISP32A16): New reloc.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	* ld.texinfo (H8/300): Add description of relaxation of
	mov @(disp:32,ERx) to mov @(disp:16,ERx).

	* ld-h8300/h8300.exp: Add new relax-7 test on ELF.
	* ld-h8300/relax-2.s: Add other direction and .w/.l variants of
	mov insns.
	* ld-h8300/relax-2.d: Update expected disassembly.
	* ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov
	@(disp:16,ERx).
	* ld-h8300/relax-7b.s: New: Likewise.
	* ld-h8300/relax-7.d: New: expected disassembly.

	* config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
	@(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
	R_H8_DISP32A16.
	* config/tc-h8300.h: Remove duplicated defines.
src-release: fix version look up for bfd based projects
2013-03-26  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* libc/stdio/local.h (_STDIO_WITH_THREAD_CANCELLATION_SUPPORT):
	New define.
	* libc/stdio/fclose.c: Use
	_STDIO_WITH_THREAD_CANCELLATION_SUPPORT.
	* libc/stdio/freopen.c: Likewise.
	* libc/stdio64/freopen64.c: Likewise.
	* acconfig.h (_FVWRITE_IN_STREAMIO): Undefine.
	* newlib.hin (_FVWRITE_IN_STREAMIO): Undefine.
	* configure.in (--disable-newlib-fvwrite-in-streamio): New option.
	* configure: Regenerated.
	* libc/stdio/fputs.c (_fputs_r): Use _FVWRITE_IN_STREAMIO to
	control __sfvwrite_r.  Add alternative implementation.
	* libc/stdio/fputws.c (_fputws_r): Ditto.
	* libc/stdio/fwrite.c (_fwrite_r): Ditto.
	* libc/stdio/puts.c (_puts_r): Ditto.
	* libc/stdio/vfprintf.c (__ssputs_r, __sfputs_r): New function.
	(_VFPRINTF_R): Use _FVWRITE_IN_STREAMIO to control vector buffer.
	(__SPRINT): Use _FVWRITE_IN_STREAMIO to control macro definition.
	* libc/stdio/vfwprintf.c (_VFWPRINTF_R): Use _FVWRITE_IN_STREAMIO
	to control vector buffer.
	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.
	* tic6xc-insn-formats.h (FLD): Add use of bitfield array.
	Add 16-bit opcodes.
	* tic6xc-opcode-table.h: Add 16-bit insns.
	* tic6x.h: Add support for 16-bit insns.
	* config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
	* gas/tic6x/insns16-d-unit.s: New test.
	* gas/tic6x/insns16-d-unit.d: Expected disassembly.
	* gas/tic6x/insns16-ddec.s: New test.
	* gas/tic6x/insns16-ddec.d: Expected disassembly.
	* gas/tic6x/insns16-dinc.s: New test.
	* gas/tic6x/insns16-dinc.d: Expected disassembly.
	* gas/tic6x/insns16-dind.s: New test.
	* gas/tic6x/insns16-dind.d: Expected disassembly.
	* gas/tic6x/insns16-doff4.s: New test.
	* gas/tic6x/insns16-doff4.d: Expected disassembly.
	* gas/tic6x/insns16-l-unit.s: New test.
	* gas/tic6x/insns16-l-unit.d: Expected disassembly.
	* gas/tic6x/insns16-lsd-unit.s: New test.
	* gas/tic6x/insns16-lsd-unit.d: Expected disassembly.
	* gas/tic6x/insns16-m-unit.s: New test.
	* gas/tic6x/insns16-m-unit.d: Expected disassembly.
	* gas/tic6x/insns16-s-unit-pcrel.s: New test.
	* gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly.
	* gas/tic6x/insns16-s-unit: New test.
	* gas/tic6x/insns16-s-unit.d: Expected disassembly.
	* faq-what.xml (faq.what.supported): Mention Windows 8 and Server 2012.
	Change sentence on native 64 bit version.
Merge branch 'cygwin' into msys2-1.0-dev