Changed SD clock speed to be 400 kHz during identification phase and 25 MHz during data phase.
Disabled 1.8V (UHS-I) mode for now as DAT line never seems to go high when operating at 400 khZ.



git-svn-id: file:///var/johncronin-svn/rpi-boot@78 0f3ef04d-8e58-4d2a-b558-b31704943fbb