Change priority of kernel message to avoid message flooding in logs.

kernel logs are flooded with info message from mdp4_overlay_mdp_perf_upd,
so changed the priority of message to debug.

Change-Id: I1ed9e7a372c563078a8127b324c05b90c67c5849
Signed-off-by: Sangani Suryanarayana Raju <csuryan@codeaurora.org>
ASoC: msm: Resume writes only for start command

For compressed and LPA drivers, set pending_buffers flag to 1 only if the client
issues a trigger_start command, not a pause_release command. This flag
is used to initiate writes to the dsp.

Change-Id: I503156863646210b460613a0b9a26a6bfb8854ed
CRs-Fixed: 442269, 449126
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
ASoC: msm: Allow drain only if a write was called

For compressed drivers, allow the drain ioctl only if
there are pending writes. Return a proper error (-EWOULDBLOCK) otherwise.

Change-Id: I4799351a8930c44d88d6968802df98896fc1531a
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
CRs-Fixed: 445370
ASoC: msm: proper error code for drain ioctl

If a drain ioctl on a compressed driver has been interrupted
by a reset ioctl, we need to return a proper error code for the
drain ioctl

Change-Id: I15f42a22b1cc13b3a0e2ae873adfcd1db2ac1e53
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
CRs-Fixed: 445370
msm: pm: warmboot entry/exit counters on IMEM

Add warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse. The debug
counters start at a memory offset of 0x664 on the IMEM. Each core
reserves 4 words for events, of which 3 are being used to monitor the
following events,
1) power collapse entry
2) warmboot exit
3) failed power collapse when wfi returns with a pending interrupt.

Change-Id: I45aac8e4a4d3421d586790b3b66fd71a8d88ea9d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm-8x60: Mark PC counters address as non-cacheable

The power collapse entry counters are incremented after the caches are
flushed during power collapse. In order for the counters to reflect the
current values, in the event of a crash, the counters have to be in a
non-cacheable memory.

Change-Id: If24a41cfa630fe0e843a4d41949ff38e1412889d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Add power collapse debug counters support.

Add platform device for PC debug counters. These counter stores the
warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse.

Usage for core0 debug counters:-
counters at address 0x2A03F664 represent no of times PC attempted.
counters at address 0x2A03F66C represent no of times PC failed.
counters at address 0x2A03F668 represent no of times warm boot happened.
no of PC attemps = PC failures + warm boot entries.

Change-Id: I3f78921f1ddd55967284fb7839a98bdb43efbeb9
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Merge "msm: pm: warmboot entry/exit counters on IMEM"
Merge "msm: pm-8x60: Mark PC counters address as non-cacheable"
Merge "msm: pm: Add power collapse debug counters support."
SoC: msm: Set soft step values to 0 to avoid noise

The abrupt steps in the curve are causing the noise. To avoid noise
smaller step size are recommended.

CRs-fixed: 439933
Change-Id: I34681af412e4f7ba8a99ce0f08f5ee1fa69186ff
Signed-off-by: Fred Oh <fred@codeaurora.org>
Merge "SoC: msm: Set soft step values to 0 to avoid noise"
Merge "Change priority of kernel message to avoid message flooding in logs."
Merge "ASoC: msm: Resume writes only for start command"
Merge "ASoC: msm: Allow drain only if a write was called"
Merge "ASoC: msm: proper error code for drain ioctl"