[stm32] SPI includes got jumbled for for DFF

DFF exists at bit 11 for f1, f2, f4 and l1, but the f0 and f3 have that bit as
CRC len and use CR2 for data size bits instead.  The merging of the F3 and F0
and attempts to put common data in common places broke the l1 code.

F3 and F0 SPI headers are still almost completely identical.
[stm32] Unify f0/f3 SPI and correct all makefiles

The common code wasn't being included in L1 builds, even though the headers now
included the correct definitions.

This combines the two f0 and f3 spi files, which previously differed only in
the number of spi peripherals defined.

Files were renamed to the full "l1f124" style, not because I like it, but
because it's the convention we have, so it's best to apply it rigourously.

Tested on L1 and F100 boards, compile tested only for others, but the examples
repository all compiles too.  (Though the lack of SPI examples for all
platforms was how this broke in the first place)
replaced placeholder __(en|dis)able_irq efm32_int functions with working ones
[timers] Fixed typo
- Bit shift should be 2, not 4 (see the datatsheet - TIMx_CMMR2 register)