target-arm: aarch64: add support for movi

This patch adds emulation for the movi instruction. This includes the
various movn, movz and movk forms.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v2 -> v3:
    - use extract32/sextract32 instead of get_bits and get_sbits
    - open code get_reg()

v3 -> v4 (ajb):
    - applied RH's constant folding comment
    - move cpu_reg allocation to top

v4 -> v5 (ajb):
    - fix comment, made invalid opcode explicit by using switch
    - ensure we invert the right one
target-arm: A64: add support for ld/st unsigned imm

This adds support for the basic forms of ld/st with an unsigned
immediate offset. This was split from the original patch from Alexander
due to re-factoring due to the changes in the decoder. This includes the
helper function:

  * do_gpr_ld
  * do_fp_st
  * do_fp_ld

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 -> v4 (pmm):
   - hoisted is_vector test into function

v4 -> v5 (pmm):
   - added support for ld/st of FP regs
   - fixed some tcg temp leaks
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60
target-arm: A64: add support for ld/st with reg offset

This adds support for the load/store forms using a register offset. This
was split out from the original patch due to re-factoring changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 -> v4 (ajb):
   fixed reg extension

v4 -> v5 (pmm):
   moved is_vector test into handle func
   fix invalid asset on opt==6

v5 -> v6 (ajb):
   fix temp lead in handle_ldst_reg_roffset
target-arm: A64: add support for ld/st with index

This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form. This was split out of
the original patch due to re-factoring changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60

---

v3 -> v4 (ajb)
   - fix ld/st reg indexed_imm to correctly extend and shift

v4 -> v5 (ajb):
   - fix silly bug with extracting register

v5 -> v6 (pmm):
   - move is_vector test into handler.

v6 -> v7 (pmm):
   - add un-scaled imm9 version

NOTES:

I suspect we're going to want to fold the 'load/store unprivileged'
insns into the same imm9 decode, so I have left the door open for that.
However since we shouldn't see those for userspace code we can ignore
it for the moment.

-- PMM
target-arm: aarch64: add support for svc instruction

This patch adds emulation for the syscall (svc) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v2 -> v3:

  - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):

  - ported to new decode skeleton

v4 -> v5 (ajb):

 - fixed stupid decode error

v5 -> v6 (ajb):
 - fix svc from peters tree.
target-arm: A64: XXX support for ldaxr and related

XXX: not up-streamable as is

I've fixed up the decoding but this is a no-op version
of exclusives so is definitely not upstreamable. Needs
rewrite.

From Alexander Graf <agraf@suse.de> aarch64 series 12/60
target-arm: A64: TODO Data processing (3 source)

Add support for various 3 source data processing instructions.

From Alexander Graf <agraf@suse.de> aarch64 series 49/60

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

---

TODO fix up attributions, commit message

v3 -> v4 (pmm):
   - ported to into new decoder
   - cleaned up to match current fn name conventions
target-arm: A64: Floating point <-> integer conv

This is kinda from suse patch 52 but I ended up rewriting
it pretty thoroughly and with a view to comments made on the mailing
list w.r.t the silliness of double stores to the fpu reg memory).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Inspired-by: Alexander Graf <agraf@suse.de> aarch64 series 52/60