msm: board-8960: Modify SMPS7 min, max voltage limits for 8960ab

PM8921 SMPS7 is the parent regulator for the LDOs which supply
to the Q6 processors. The worst case voltage for Q6 processor
on 8960ab is 1.075V (compared to 1.05V on 8960). Raise the S7
voltage constraints from 1.15V to 1.275V in order to accommodate
the increase in Q6 supply voltage.

CRs-Fixed: 507062
Change-Id: If3e249b6412d141d7108332b43481e127c350bb2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
USB: EHCI:  Ensure 10 msec delay between bus states

According to EHCI specification, software must wait for at least 10 msec
after a port indicates that it is suspended before initiating a port
resume.  The current code uses jiffies and fails to give the delay if
suspend and resume happens at the timer tick boundaries.

The correct implementation would be ensuring this delay by using hrtimers
or ktime_get().  This involves changing many drivers.  Hence workaround
it by increasing the state change delay to 2 jiffies.

CRs-Fixed: 521047
Change-Id: I703210cca83d649d1b253e971dfba8f62c6ccb8c
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
msm: spm: modify power collapse seq for kraitv3

High sleep current observed due to L2 cache not going into
power collapse in special cases.

While analyzing, a timing issue was found that can manifest itself when the
clamp signal is asserted during the Krait CPU1 power collapse sequence.
When it occurs, the issue causes an L2 FIFO to falsely believe that it
has data to return to CPU1 when it does not.The condition isnt detected until
later when CPU0 and the L2 attempt to collapse.

This condition keeps the L2 from going idle which keeps it from power
collapsing after both CPUs have collapsed.  This in turn prevents the
RPM from enabling a system low power state (VDD minimization).
The issue is likely process/temp/voltage dependent.

HW team recommended a workaround, the details are as below.

Add commands to the Krait CPU power collapse SPM sequences to assert
Krait CPU reset prior to asserting the CPU clamp signal and de-assert
CPU reset after the CPU clamp is asserted.
Since the CPU clocks are gated (by the first SPM command in the
sequence), and the clamp is applied, the Krait CPU will do nothing
when its reset is de-asserted.

The workaround involves changing both CPU power collapse SPM sequences
(Power Collapse with and without RPM notification).

CRs-fixed: 518750
Change-Id: I62c76f49a96a8cb6ecf67733ae9a7ff1a79a76f7
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Merge "msm: camera: Notify application in case of bad state."