Added testbench for fir filter

Also changed the code of the fir_filter a bit based on what I saw in the
testbench, just a few obvious coding errors:
- Shift of delay line registers off by one,
- DACstb set the wrong way around, and not unset at all
- on first accumulator setting need to set to lower 32 bits to the
result of the multiplication and the upper 3 bits to 0
- Mulitply step bit shouldn't fire on the same process step as the delay
line shift bit; otherwise the first accumulator settings won't be done
yet...

Now I can't see any simple/obvious problems by running simulations
anymore, so ready for proper testing in lab tommorow.... fingers crossed
like the other two times, it miraculously works!...