Synchronizing HDL

* On the path to timing closure; I've buffered most of the control
  lines across clock domains.
* Still to do: reset module, dac_clock/dac_2xclock phase constraint
* New duc_enable flag lets you turn off including the Digital Up
  Converter DSP from the final verilog output.
* New simple APB3 slave and simulation.  Testing on device also a TODO.