core_logic: update to reflect board changes
core_logic: add reset logic

Add an opcode for the MCU to reset some internal registers as well as the
coprocessor.

The SPI state machine registers should not be reset this way since the reset
opcode depends on them.  They have their own reset mechanism.
core_logic_test: Test read/write of registers

Add logic to read out the register values.
Test read/write from both sides.
core_logic: specify initial register values
core_logic: Add logic to hand over control of RAM bus

When executing an RPC operation, let the coprocessor have control of the
RAM bus.
core_logic: tri-state MISO during external reset

When the coprocessor is being reset by the in-system programmer, tri-state
the MISO line to avoid a bus contention.  This involves turning the
coprocessor reset into a bidirectional I/O to detect an external reset.
core_logic_test: Test coprocessor RAM access
core_logic: fix coprocessor RAM access logic