APPLIED: spi: tegra: clear RDY bit prior to every transfer

The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin <yelin@nvidia.com>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: accept any SKU ID for most chips

For Tegra20, the SKU ID actually impacts how U-Boot programs the chip,
and hence we need to explicitly know about each and every SKU ID in order
to operate correctly.

However, for Tegra30/114, this isn't the case. Rather than forcing each
new user with a different SKU to manually add their SKU ID into the code,
simply accept any SKU ID.

If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll
need to undo this, or make the default case map to conservative defaults,
but for now it's likely the path to least support cost.

Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
fdt: make fdt_fixup_memory_banks dynamically size tmp array

The array of banks passed to fdt_fixup_memory_banks() might not be the
same as U-Boot's internal array of memory banks. For example, if some
memory is reserved for simplefb, one of U-Boot's banks might need to be
split into two pieces when passed to the kernel. Hence, it's invalid to
assume that CONFIG_NR_DRAM_BANKS is the correct size for any array of
memory banks passed to the kernel. Instead, size the array dynamically
so that any number of banks will work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
lcd: implement lcd_adjust_memory_banks()

If simplefb is used, then the RAM used for the FB data cannot be used
by the OS as regular RAM; instead, it must be carved out of the memory
banks passed to the kernel. This patch implemnts a function that will
delete, split, or resize the entries in U-Boot's list of memory banks
so that the list of banks passed to the kernel doesn't include the FB
memory.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: fdt: use lcd_adjust_memory_banks()

If simplefb is enabled, then before calling fdt_fixup_memory_banks(),
pass the array of banks through lcd_adjust_memory_banks() to make sure
that the FB memory region isn't passed to the kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add simplefb DT node during bootz/m

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra: T1x4: SPI: Use a common name (t1x4) for SPI driver

Tegra124 is compatible w/T114 SPI, so try to commonize as
much as possible.

TEST=built all T1x4 boards, tested on Venice1 & 2 OK.
There's no real binary change here, just names/includes.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114: Add support for more clock sources for T1x4 periphs

Some T1x4 peripherals can take up to 8 different clock
sources (parents), including 4 new ones that don't exist
on previous chips (PLLC2/C3/MEM2/SRC2). Expand clock/pll
code/tables to support these additional bits/sources.

Changes were made to some common code. Testing on T30/T20
showed no changes in periph clock sources/divisors.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I396169cd5732ad42aeddefa70fc43f79e969a70d
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114: spl: Set system clock to clk_m

Based on Tegra114 TRM, system clock can run up to 275MHz. On power on,
the default sytem clock source is set to pllp_out0. In function
clock_early_init(), pllp_out0 will be set to 480MHz which is beyond system
clock's upper limit.

The fix is to set the system clock to CLK_M before initializing PLLP.
Tested on A02 dalmore board.

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114: Dalmore: Add voltage reg/PMIC init for various periphs

These powerrails are currently needed for kernel boot. This will
be move to a pmic-specific driver (or even better moved to the
kernel) at a later date.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: Id1654e6338b11cb22715fa3caba644cfe6e2410b
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add arch-tegra124 include/header files

No real HW change on T124 for 90% of the toys, so just include
a common T1x4 header file (based on T114 headers), and if a new
register/bit is needed, add it at the end. Some headers (clk_rst,
clock-tables, pinmux, etc.) had too many changes in structs,
devices, etc. added/removed, so they are added as complete new
files for T124, and can be diffed against T114 headers to see
what's changed (again, not a lot).

In a future (RSN) patch I'll point the T114 headers at the
new common tegra1x4-xxx files, too.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add changes to common arch-tegra header files

Minor changes to support T124 chip and sku IDs.

Change-Id: I44092a2ec558e01952be8cc7c0534e384a810ffd
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add SPL/AVP (arm720t) cpu files

This provides SPL support for T124 boards - AVP
early init, plus CPU (A15) init/jump to main U-Boot.

Change-Id: I721f83f1d5fa549e0698e0cc76ab3e5ea11ba895
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add CPU (armv7) files

These files are for code that runs on the CPU (A15)
on T124 boards. At this time, there is no A15-specific
code here. The warmboot/LP0 files aren't included as
that code hasn't been ported yet.

Change-Id: I299409ca1b051f8a76df641be73f1f4489d491ab
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add common CPU (shared) files

These files are used by both SPL and main U-Boot.

Change-Id: I5b762fc3f9886f588372c7706feaf80c50305c75
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add generic T124 build support

Basic Tegra124 build support added - no specific
board is targeted.

Change-Id: Id16b44b5b394e03b121e702eaef2f49f55ab3da3
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Venice2: fdt: Add device-tree files

These are fairly complete, and near-clones of T114 Venice,
with an additional I2C port, and MMC address changes for T124.

Change-Id: Icf9d34a2ebf15b5389bbc5293a067a08938ef16a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124: Add Venice2 (T124) build

These are the board files for Venice2 (t124), plus the AS3722
PMIC files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio
and display and WB/LP0 are not supported yet.

Change-Id: Ic9f023c0d62e2ee24b9189d93e61c2f492e568fd
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
config: tegra124: usb: ehci: Fix "bootp" issue

Fix the timeout issue after running "bootp" command in u-boot
console.
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).

BRANCH=none
BUG=chrome-os-partner:23539
TEST=install USB LAN device to USB3 port (closer to LCD panel of
Tegra124 Venice2 platform) Connect LAN cable. Run "usb reset".
Run "bootp". No EHCI timeout error.

Change-Id: I2f1a45b86388cbd814bd41a79a51bcbe3f8b3489
Signed-off-by: Jim Lin <jilin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/174505
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arm: tegra: Fix the CPU complex reset masks

The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>