fixed getter/setter for reset/clock
no arg setter for reset, reset->resetVal in Reg, updated tests
generalized Mux1H to <: Data rather than <: Bits, and Vec inputs
Surround creation of top level module when invoking from sbt
Better handle nested exceptions
More robust cloning of Data. Better error reporting.
Fix Regs in Mem for sequential reading of bogus data
Cleanup if/else logic
Cat needs to accept more types and always return a UInt
Make Decoupled/Valid match, bring back ValidIO
Stop infinite recursion in SInt.===
fix Valid in NameTest
Merge branch 'reference-port-v2' of github.com:ucb-bar/chisel into reference-port-v2