Merge pull request #18 from smirolo/v1.1

fix in v1.1 branch: module prefix added twice
Don't turn Vec into ROM unless width is known
Don't include Literals in VCD
Merge branch 'master' into v1.1
Merge pull request #19 from smirolo/v1.1

fix - do not print literal in vcd
Fix swapped definitions of (UFix / Fix) and (UFix % Fix)
Don't fold signed operators

The folding code is only correct for unsigned operations.
For C++, specify mul/div destination width

This allows the destination width to be set independently of the input widths.
Implement signed-by-unsigned mul/div in terms of signed-signed mul/div

Verilog doesn't natively support these operations directly, so we were generating incorrect code.
Added asDirectionless method. Used to strip directions from intra-component FIFOIO wires, i.e. a workaround for component stack weirdness with bundle parenting
cleaned up detection of user code, made recompatible with nodes outside of components
filter-in only public methods out of getDeclaredMethods to support lazy declarations in Component subclasses as generated by scala 2.10