mesa: Return ZeroVec/dummyReg instead of NULL pointer

Assertions are not sufficient to check for null pointers as they don't
show up in release builds. So, return ZeroVec/dummyReg instead of NULL
pointer in get_{src,dst}_register_pointer(). This should calm down the
warnings from static analysis tool.

Note: This is a candidate for the 9.1 branch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
r600g: Fix build

Broken since 2840bec56f79347b95dec5458b20d4a46d1aa445 when opencl is
disabled.
radeonsi: rename SI chip class from TAHITI to SI

Covers the entire family.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: initial support for CIK chips

Add the infrastructure to differentiate them.
Just treat them like SI for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: initial PM4 changes for CIK

note which packets are removed and add new ones.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: register updates for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: emit TA_BC_BASE_ADDR_HI for border color on CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: emit additional shader pgm rsrc registers for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: properly handle DB tiling setup on CIK

On CIK, DB switches back to using per-surface tiling
parameters rather than the tile index used on SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: store chip class in the pm4 struct

Will be used for asic specific pm4 behavior.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: update surface sync packet emit for CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: PA_CL_ENHANCE is privileged on CIK

Needs to be and is set by the kernel.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: emit PA_SC_RASTER_CONFIG[_1] on cik

Use the golden values for each asic.

Todo: update Kabini and Kaveri.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: add llvm processor names for CIK

Requires updated llvm.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: disable 2D tiling on CIK for now

Causes GPU hangs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: add bonaire pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeonsi: add kabini pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
i965: Split surface format code into a new file (brw_surface_formats.c).

brw_wm_surface_state.c has gotten rather large and unwieldy.  At this
point, it consists of two separate portions:

1. Surface format code

   This includes the giant table of surface formats and what features
   they support on each generation, as well as the code to translate
   between Mesa formats and hardware formats.

   This is used across all generations.

2. Binding table (SURFACE_STATE) related code.

   This is the code to generate SURFACE_STATE entries for renderbuffers,
   textures, transform feedback buffers, constant buffers, and so on, as
   well as the code to assemble them into binding tables.

   This is only used on Gen4-6; gen7_surface_state.c has Gen7+ code.

Since the two are logically separate, and one is reused on every
generation while the other is not, it makes a lot of sense to split
them out.  It should also make finding code easier.

No code is changed by this patch.  I simply copied the file then deleted
portions of both.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i915: Remove GEN >= 4 extension support

This copy of the source file is only used for GEN <= 3, so remove the
dead code.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>