i965/blorp: Use passed in framebuffer rather than ctx->DrawBuffer

We have the destination framebuffer object passed in; there's no need to
go digging around in the context.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: compute DDX in a subspan based only on top row

Consider only the top-left and top-right pixels to approximate DDX in a 2x2
subspan, unless the application requests a more accurate approximation via
GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the
new driconf option disable_derivative_optimization.

This results in a less accurate approximation.  However, it improves the
performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0%
confidence) on Haswell.  No noticeable image quality difference observed.

The improvement comes from faster sample_d.  It seems, on Haswell, some
optimizations are introduced to allow faster sample_d when all pixels in a
subspan have the same derivative.  I considered SAMPLE_STATE too, which allows
one to control the quality of sample_d on Haswell.  But it gave much worse
image quality without giving better performance comparing to this change.

No piglit quick.tests regression on Haswell (tested with v1).

v2: better guess for precompile program key

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
r600g/llvm: fix txq for texture buffer
r600g/llvm: Undef z and w component of 2D TXP inst
r600/llvm: Adds support for MSAA
i965: fix bogus swizzle in brw_cubemap_normalize

When used with a cube array in VS, failed assertion in ir_validate:

   Assignment count of LHS write mask channels enabled not
   matching RHS vector size (3 LHS, 4 RHS).

To fix this, swizzle the RHS correctly for the writemask.

This showed up in the ARB_texture_gather tests, which exercise cube
arrays in the VS.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
mesa: add texture gather changes

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: add texture gather changes

V2 [Chris Forbes]:
   - Add new pattern, fixup parameter reading.

V3: Rebase onto new builtins machinery

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: add SHADER_OPCODE_TG4

Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().

V3: Updated for changes in master.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Add support for ir_tg4

Lowers ir_tg4 (from textureGather and textureGatherOffset builtins) to
SHADER_OPCODE_TG4.

The usual post-sampling swizzle workaround can't work for ir_tg4,
so avoid doing that:

* For R/G/B/A swizzles use the hardware channel select (lives in the
   same dword in the header as the texel offset), and then don't do
   anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
   channels instead of sampling.

V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vs: Add support for ir_tg4

Pretty much the same as the FS case. Channel select goes in the header,

V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
glsl: flag shaders which use gather4 at all

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: w/a for gather4 green RG32F

V4: Only flag quirks if there are any uses of gather in the shader,
    to avoid spurious recompiles just because someone happened to use
    RG32F.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add BRW_SURFACEFORMAT_R32G32_FLOAT_LD, required for IVB gather4 w/a

gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:

   - use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
   - select BLUE channel to read GREEN

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: make room in the binding table for a full alternate set of surface_states

Worst-case is that *every* texunit uses a format that needs overriding.

V4: Place the gather slots last, so shaders which don't use gather don't
    get penalized by having a huge binding table.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Emit a second set of SURFACE_STATE for gather4 from textures.

This allows us to use a different surface format for gather4, which is
required for R32G32_FLOAT to work on Gen7.

V4: - Only emit alternate surface state for shaders which will actually
      use it.
    - Pass a simple 'for_gather' flag rather than a function pointer.
      The callee can decide what w/a to apply.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: use gather slots in the binding table for gather4.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Enable ARB_texture_gather on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/hsw: Apply gather4 RG32F w/a using SCS instead of shader.

The new surface channel select bits allow us to avoid having to
recompile the shader for this workaround.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>