pcie_fpga: fix some reset signals usage.
pcie_fpga: Make the testbench DDR DMA transaction bigger to catch more
FIFO overflow related errors.
pcie_fpga: Fix reset signals for DDR core.
pcie_fpga: Add status bit in GSR register signalling DDR_memory_ready
status.
pcie_sw: Check if DDR memory is working at all before issuing DMA test
pcie_fpga: Add dynamic support for both INTA and MSI interrupts. Switch
to PCIe core cfg_* interface for generating interrupts.
Merge remote-tracking branch 'ohwr/master'
Merge branch 'master' into pcie-test
hdl/platform/virtex6/*: add chipscope 6 port
hdl/modules/*/wb_acq_core/*: (1/5) add data acquisition module

This module allows storage of samples from a streaming data source
on the following modes:

1) Simple acquisition on request
2) Pre-trigger acquisition
3) Post-trigger acquisition
4) Pre+Post-trigger acquisition

Also, two acquisition variations are possible:

1) Single-shot (one time) acquisition
2) Multi-shot (multiple times) acquisition

There are a lot of improvements and fixes to be done!
This is work in progress!

The design was partially based on the original HDL module
fmc_adc_100Ms_core from the fmc-adc-100m ohwr repository
(http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository)
hdl/modules/dbe_wishbone/*: (2/5) add data acquisition module

Add wishbone top modules to the central dbe_wishbone_pkg
package
hdl/modules/dbe_wishbone/*: (3/5) add data acquisition module

Add "wb_acq_core" folder module to the Manifest file
hdl/sim/regs/*: (4/5) add data acquisition module

Add simulation register definitions
hdl/sim/regs/*: (5/5) add data acquisition module

Add testbenches for the acquisition module
hdl/top/pcie/bpm_pcie_ml605.vhd: comment out signals

This was necessary, in order to use an external set
of DDR3 UI signals
hdl/platform/*/Manifest.py: fix wrong pathname
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/*: add wb_acq_core module

This commit adds the data acquisition core to the pcie design
to demonstrate DMA read/write from the SDRAM
hdl/modules/*/wb_acq_core/*: move declarations to dbe_wishbone_pkg
dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd: fix stall logic

We must only get new data from the fc interface when we are
not stalled. This is necessary due to the one cycle-long
delay between stall assertion by the fc_source modules
and the registration and preparation of the inputs
dbe_wishbone/wb_acq_core/fc_source.vhd: fix stall assertion

The assertion of the stall and dreq signals was not registered
on output. This was causing timing errors. Also, the stall signal
was being asserted one cycle before the necessary. Because of this,
modules that relied ont this behaviour must be changed.