aarch64: Implement simd NEG.

This implements the simd vector and scalar NEG variants.
aarch64: Fix vector MOVI 64-bit vector variant bit numbering.

The bits specifying bytes go in the same order, not reversed.
aarch64: fix simd movi decoding for floating-point immediates.

Floating-point vector loads were being translated as ORR instructions.
aarch64: Implement simd FDIV.

Also rename handle_simd3su0 to handle_simd3s and alter the function
comment accordingly, since both U=1 and U=0 cases are handled there.
Merge pull request #1 from jtb20/aarch64-1.6

Thanks