Re-add "memory" back to clobber lists where CMPXCHG instructions are used.
Note this instruction with LOCK prefix implicitly serializes load/store.
Try to improve performance on i486 class CPUs.

- Partially revert r253876. [1]
- Use conditional jumps instead of function pointers. [2]  Note this change
may break KPI, i. e., atomic_load_acq_64() and atomic_store_rel_64() are now
real functions.

Note this changes are not tested because I do not have i486-class CPUs.

Objected by:		attilio [1]
Suggested by:		bde [2]
Remove "memory" from clobber list for atomic_swap_64_i386().  This function
does not have any variants with memory barriers.
MFC:	r254379

Avoid potential redefinition of the macro.
MFC:	r254384

Simplify check for CMPXCHG8B instruction.  Note CMPXCHG8B instruction is
always available for Rise mP6 processors although it is not set by CPUID.
- Optimize atomic_cmpset_64_i386().
- Move all 64-bit atomic functions to atomic.h.

Suggested by:	bde
Restore atomic_cmpset_int() for CPU_DISABLE_CMPXCHG case as well.
Micro-optimize atomic_cmpset_64_i386().