Merge branch 'master' of https://github.com/fnoble/Swift-Nav-Code
Merge remote-tracking branch 'colin/master'

Conflicts:
	tests/acq/acq_test.c
Hash initialization stuff, flash configuration writing stuff,
DMA rx debug stuff
Changed usart_n_read_dma so that if it is called and NDTR has
rolled over without yet triggering the interrupt that increments
wr_wraps (leading the apparent number of samples that have been
written to be less than the number that have been read from the
queue), it will return 0.
This should have been included with the last commit, need to have
the state in debug process messages be uninitialized so that it
can retain its state until the next call in case NDTR rolls
over without wr_wraps being incremented when uart_n_read_dma
is called and after reading some part of the packet it is unable
to read the rest of the packet within the same
debug_process_messages call.
Changed error.c so it uses USART6 instead of 1
RX DMA bug fixes.
In usart_rx the interrupt service routine wasn't checking the
correct interrupt status register and was clearing the wrong
flag register (LISR instead of HISR in both cases). Also, when
calculating the number of bytes available in the RX buffer, due
to a delay between the rollover of the NDTR register and
the flag going high (I think that's what it is), it
is possible for there to appear to be a negative number of bytes
available in the buffer (underflow). This was causing the
subtraction of the u32's to wrap and trigger the overflow condition
and go into speaking death. This is accounted for by using s32's
and just returning 0 if the subtraction is less than 0.
TX DMA bug fix.
We were getting FIFO errors and randomly inserted '0x00' bytes in
direct mode and in FIFO mode with single transfers, it seems that
this was due to the memory bus not being available to the DMA after
enabling a DMA transfer. Changing to FIFO mode with bursts of 4
bytes transfers seems to have fixed this - no more inserted '0x00's
that I have seen. There are still some FIFO errors but at this point
not sure if they are an issue.
Adding files as they are before finishing up flash validation
and cleaning up - seems like flash reading is working properly now
with DMA TX bug fix.
Writing flash configuration seems to work as well but need validation
to be sure.
Flash reading and validation seems to work now, need to clean up a bit
Some cleanup of flash.py and fpga_flash.py
Going to move some of the verification stuff from fpga_flash.py
into functions in flash.py
Update python correlation function for s8 code.
Add prn property to access prn in channel measurement.
Update repr for nag and chan measurements.
Flash writing and reading seem to be working appropriately
now when running fpga_flash.py, compatible with HDL commit
5497debe48c4cea3556538f892a91af6649a57af
Flash writing, reading, and verification working
Removed unnecessary prints from read callback
Cleaning up flashing stuff and making printing prettier
Changed serial_link.py so portNotOpenError isn't thrown when you
call SerialLink.close()
Integrated hex flashing script in fpga_flash.py into __main__ of
flash.py