Adjust the processor for the cache

I made my best guess at the changes needed to the processor to support
the single cycle accesses needed.

It all seems right, except that the PC register is currently qualified
by the ID_Stall signal, which suggests that I haven't done enough.
What happens if ID_Stall goes false but the instruction memory is still
stalled?  It should work, `cause it does now, but it doesn't look
right.