Okay, I buy that. I guess doing 32 extra float-point transfer instructions is pretty high overhead for most unwinding.

Next question then.  The way I implemented the VRS for the floating point attempted to mimic the overlapping register behavior in VFP.  Specifically S0,S1 use the same memory buffer as D0 in Registers_arm, etc. This was under the the compiler might (stupidly) generate code that made 2 single-precision stores in S0 & S1 in order to compose a value in D0.

For example, I couldn't find anything in the spec that would disallow the moral equiv of:
   double d = 1.3；
  _Unwind_VRS_Set(context, _UVRSC_VFP, UNW_ARM_S0, _UVRSD_UINT32, 
                               &d);
  _Unwind_VRS_Set(context, _UVRSC_VFP, UNW_ARM_S1, _UVRSD_UINT32, 
                               reinterpret_cast<uint8_t*>(&d)+4);

to do the equiv of

  _Unwind_VRS_Set(context, _UVRSC_VFP, UNW_ARM_S1, _UVRSD_UINT32, 
                               reinterpret_cast<uint8_t*>(&d)+4);

or vice versa? It seems unlikely, but could be possible.

Anyways...if that's allowed, what's the right loading sequence?  Can we just consider the register set to be a bunch of single-precision floats and execute a set of FLSTMs for each dirty register?  Or do we need to remember that the VRS_Set was called with single-precision sometimes but double-precision other times and match that up with FLSTM versus FLDTM?