Add uTCA AMC board device ID
Always enable Bus Master capability
Change the PCIe BAR sizes.
This is needed because on some boards (namely CCT) we get *only* something
like 2 MB of memory range for each device. The solution is to change
BARs size and use paging (sigh...)
Introduce paging mechanism when addressing DDR SDRAM or Wishbone
endpoint.
Update testbench
Properly present DMA capabilities in PCIe driver
Fix Wishbone BRAM generation for synthesis
Fix reset signals scheme for DDR core
Add all IP cores for ML605 board Virtex6 FPGA.
Add support for generating firmware for ML605 board.
This includes adding necessary hdlmake Manifest files,
VHDL top file and constraint definitions.
Also, add xise project file and .gitignore for health safety.
Fix DMA buffer area declaration
Fix shifting of address passed to the DDR controller.
Old code assumed specific fixed DDR_PAYLOAD_WIDTH/DDR_DQ_WIDTH ratio,
which is true for the 7 series (at least Kintex & Artix), but is
different for Virtex6 series.
Fix endianness issues for DDR memory with DMA transactions
Fix clocking parameters for Virtex6 DDR core to always use 200MHz clock inputs
Update software test:
- add test for paging mechanism
- update used BAR ranges to match changes in FPGA firmware
- properly check DMA transaction status instead of waiting ridiculous
  time periods
- minor cleanups
Add benchmark for testing PCIe data transfer rates.
Currently direct IO and DMA transfers from BAR2 (onboard DDR memory) are
tested.
Fix variable assignment when polling for DMA status