Merging r196189:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196687 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196190:
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r196190 | jiangning | 2013-12-02 17:29:32 -0800 (Mon, 02 Dec 2013) | 2 lines

Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196688 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196191:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196689 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196192:
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r196192 | jiangning | 2013-12-02 17:33:52 -0800 (Mon, 02 Dec 2013) | 2 lines

Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196690 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196198:
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r196198 | haoliu | 2013-12-02 19:39:47 -0800 (Mon, 02 Dec 2013) | 3 lines

AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196691 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196199:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196692 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196208:
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r196208 | haoliu | 2013-12-02 21:58:30 -0800 (Mon, 02 Dec 2013) | 3 lines

AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196693 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196209:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196694 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196211:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196695 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196359:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196696 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196360:
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r196360 | kevinqin | 2013-12-03 23:53:28 -0800 (Tue, 03 Dec 2013) | 1 line

[AArch64 NEON] Add missing compare intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196697 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196361:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196698 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196362:
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r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line

[AArch64 Neon] Add ACLE intrinsic vceqz_f64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196699 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196456:
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r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines

For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
Merging r196533:
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r196533 | apazos | 2013-12-05 13:07:49 -0800 (Thu, 05 Dec 2013) | 3 lines

Implemented vget/vset_lane_f16 intrinsics


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Merging r196535:
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Merging r196588:
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r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines

Bug 18149: [AArch32] VSel instructions has no ARMCC field

The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.

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--- Reverse-merging r196668 into '.':
U    lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
U    test/Transforms/InstCombine/addrspacecast.ll



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Merging r196637:
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r196637 | arsenm | 2013-12-06 18:58:41 -0800 (Fri, 06 Dec 2013) | 1 line

Add getBitCastOrAddrSpaceCast
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Merging r196668:
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