implement tempcontrol

tempcontrol: sysfs interface for temp sensor threshold control

tempcontrol: always show current temp in sysfs

temp control: setting templimit to 0 will revert to kernel default

tempcontrol: set initial sysfs value to kernel default
Revert "Increase the maximum temperature treshold."

This reverts commit a182bec66188381ab59867fa49ecd81a8a15fb54.
make tempcontrol optional (introduce config variable)
build flags: remove -fsingle-precision-constant from KBUILD_CFLAGS
deadline: Allow 0ms deadline latency, increase the read speed

Change a timer compare from after to after-equals, thus allowing
0 timeout and making deadline schedule FIFO.

Signed-off-by: xiaobing tu <xiaobing.tu@intel.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
SIOplus: Allow 0ms deadline latency, increase the read speed

Source: previous commit
OMAP4: cpuidle: don't touch mpu and core state until CPU1 is off

MPU/Core logic and PD states shouldn't be changed until CPU1 is
completely off

Change-Id: Ia90126776e7bd7108c7b885c622df36323982cb0
Signed-off-by: Lianwei Wang <lian-wei.wang@motorola.com>
Signed-off-by: suilunlam <a0868997@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
OMAP4: PM: Program pwrst of each pwdm as per their supported state

Configure next power state of each power domain based on their
supported state. This will be done one time during initialization of
power_setup function. Device can change their power domain state runtime
based on dev latency requirement.
Also, this API will be called during suspend path as well to make sure each power
domain has been configured the right state before entering OFF transition.

Change-Id: I030f2b5df3186cb147e919d9d98dbcdfc75269a8
Signed-off-by: Gilles-Arnaud Bleu-Laine <gilles@ti.com>
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP4: PM: Regulator: suspend prepare and finish call.

Before entering suspend configure regulator resource to desired
state.
While resuming from system wide suspend, the  un-connected regulator
resource's are not turned off. By calling regulator_suspend_finish, it
ensures that resources will be gated if the usecount = 0.

Change-Id: I0cff12f24b1c0879fdb27e079baf1c6793f5a1d3
Signed-off-by: Ambresh K <ambresh@ti.com>
OMAP4: PM: Re-factor configuring pwrst settings

Refactoring configure_pwrst to allow setting of pwrdm states from init
and suspend path as well.
This takes care of:
- Allow achievable state to be programmed from init and suspend path
- Error if pwrdm state is not set.
- Remove duplication of code.

Change-Id: I1a42566cc83d67b870e9fe1076522ea8ce7ccb4a
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP4: PM: Correct powerstates initialization sequence

  During initialization of new powerstate item it
should be added into list before it's configuration.

  Initialization of powerstates skiped for CORE, MPU,
CPU0, CPU1 powerdomains. Current implementation caused
incorrect initialization of powerstate at least for
GFX PWRDM because it masked by CORE PWRDM.

We should add powerstate node to list before it will
been initialized.

Change-Id: I2f9274a9ec951eb9f6b54e104a0e14921b61264e
Signed-off-by: Volodymyr Riazantsev <v.riazantsev@ti.com>
OMAP4: PM: fix for "re-factor configuring pwrst setting"

The error has been admitted in merge branch 3ae032677.
The additional source code in function pwrdms_setup(...)
was added in patch "OMAP4: PM: Re-factor configuring pwrst
settings" commitId faa96477.

Change-Id: Ie0d5efbaa41e7b5eab361292d621b8fe98bd69ec
Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
OMAP4: PM: setup initial OPP configuration

pm.c setups the initial voltage and frequencies for init devices
on bootup to be careful of invalid device configurations by
custom bootloaders. However, DVFS data structures are not aware
of these - As a result, when doing the first time scale of
a differnt device we could have a following scenario:

At boot - MPU,IVA,Core at OPP100

after pm framework has completed initialization, lets say IVA/AESS
transitions to OPP50, DVFS framework does not have information about
the OPP current frequency/voltage of IVA/MPU and sees that only
IVA is requested, moves the IVA and core to OPP50. This configuration
is invalid as MPU is currently at OPP100 and device should not have
scaled core to OPP50 without looking at OPP100 configuration of
MPU.

To resolve this, we populate the dvfs data structure with the
requisite init devices' frequency configuration by doing a
omap_device_scale.

Change-Id: Ib3048fb7fadec5adabbbcbce56c1ead026953de6
Reported-by: Hemanth V <hemanthv@ti.com>
Tested-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: PM: Fix missed PRCM MPU interrupt events

OMAP PRCM detects events with EDGE sensitivity. Edge sensitivity
requires to clear the interrupt event status bit before acknowledging
the source event.
If the source event is cleared (1) before reseting the interrupt event
status bit (2), then a subsequent source event (i.e edge) between (1)
and (2) would be missed. Then, all the source events would be kept
"masked" until the source event is cleared again.

The bug seen here is that upon two consecutive PRCM interrupt events
from the IO daisy chain source event, the second event is missed if it
occurs before the PRCM interrupt event status is cleared.
Since the IO daisy chain source event has not been acknowledged, the
subseqent events from this source are missed too.

This patch fix the PRCM interrupt handler by acknowledging the interrupt
event status bit before clearing the source event.

Change-Id: I8c43a93c3b6c7c654ddaa262b7c1c3e7385da158
Signed-off-by: Patrick Combes <p-combes@ti.com>
Signed-off-by: Cedric Poignet <c-poignet@ti.com>
OMAP4460: TWL: disable PD on VCORE1 shutdown

When the PREQ goes low, both VCORE1(VDD_CORE) and VDDD_MPU
start transitioning to 0 volt but VCORE1 discharge is faster
than VDD_MPU discharge. This causes reliability concern from
OMAP's perspective. So, we disable  pulldown on VCORE1 to
slow down VDD_CORE discharge to make it comparable to VDD_MPU.

The Pulldown does not impact DVFS transition, and actual
OFF timing is not changed as well.

Change-Id: I707bb4c4ae50b3452304180e6b42db6b2bfdedd9
Signed-off-by: Nishanth Menon <nm@ti.com>

Conflicts:
	arch/arm/mach-omap2/omap_twl.c
OMAP4: Enable main inst clock for save to ram.

In HS-devices we must ensure that l3_main_inst
clock is enabled for saveram operation

Change-Id: Id9a5ab013ed99499f0fde89d9251ae5a95a49b45
Signed-off-by: Axel Haslam <axelhaslam@ti.com>
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Chittim Madhusudan <c-madhu@ti.com>
OMAP4: PM: Fix L3INSTR/IVAHD save/restore context logic

The L3INSTR/IVAHD contexts are restored
when MPU is going through both OSWR and OFF states
on HS/EMU devices (not only OFF state).

Change-Id: I516a9e88932485f6d77c529602647f7199fa7212
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
ARM: OMAP4: l2x0: Cleanup prefetch offset register setting

The bits [31:5] of Prefetch Offset Register are reserved in
PL310 r2p0 so they should be kept unchanged.
It's enough to set Data prefetch enable bit in PL310 auxiliary
control register to enable the feature, so setting of bit 28 of POR
is removed.
Before writing POR value, the bits [4:0] has to be cleared to remove
previous value.

Change-Id: Id5d047da0daa0c841c69d4d587d2280d2f3433f9
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
ARM: OMAP4: l2x0: Set optimized value for prefetch offset

Tuning the value of prefetch offset register of PL310 cache controller
for OMAP4 family. The patch can give up to 4% better results in low level
benchmarks (like bw_mem at block size above 2 Mb) and up to 2% in benchmarks
imitating use cases (like Sunspider).
Note: if double line fill is enabled, the optimal value can be different.

Change-Id: Iba7b7b5950981b851c4eac4ed636ec5d8006c87b
Signed-off-by: Konstantin Shlyakhovoy <x0155534@ti.com>
remove simple GPU governor

It wasn't working properly.