patched memory leak, 2 levels 1 octave at a time, hardcoded fishoil matching
added UART to SOPC, removed HW divide, timer, and lowered SDRAM clk to 90 to meet timing
UART test on Nios working, SDRAM clks at 90 don't appear to cause timing issues, but should watch this as timing analysis shows negative slack
forgot to add new uart files