Added  TBs for modules, check commit msg. MP

add_rkey, inv_mix_bytes, mix_bytes, mix_cols, shift_rows, sub_bytes:
Registers can't be used in an assign statement. Just does not make sense
physically in HW.

stream_in: The size for the signals tin, tin_r, and tout should be 2
bits wide instead of 1 bit wide.

key_expansion_logic: Changed key_out from input to output. Not sure how
this was tested without any outputs.

cipher_core: changed a few signals from reg to wire because logically
they are wires and not registers.