Turn AMDGPUSubtarget::getDataLayout into a static function.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197310 91177308-0d34-0410-b5e6-96231b3b80d8
Turn NVPTXSubtarget::getDataLayout into a static function.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197311 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor NVPTX's computeDataLayout.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197312 91177308-0d34-0410-b5e6-96231b3b80d8
Convert register liveness tracking to work on a sub-register level instead of just register units.

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197315 91177308-0d34-0410-b5e6-96231b3b80d8
[Stackmap] Only the AnyReg calling convention should preserve all registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197316 91177308-0d34-0410-b5e6-96231b3b80d8
[Stackmap] Liveness Analysis Pass

This optional register liveness analysis pass can be enabled with either
-enable-stackmap-liveness, -enable-patchpoint-liveness, or both. The pass
traverses each basic block in a machine function. For each basic block the
instructions are processed in reversed order and if a patchpoint or stackmap
instruction is encountered the current live-out register set is encoded as a
register mask and attached to the instruction.

Later on during stackmap generation the live-out register mask is processed and
also emitted as part of the stackmap.

This information is optional and intended for optimization purposes only. This
will enable a client of the stackmap to reason about the registers it can use
and which registers need to be preserved.

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197317 91177308-0d34-0410-b5e6-96231b3b80d8
Remove weak vtables. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197323 91177308-0d34-0410-b5e6-96231b3b80d8
[Powerpc darwin] AsmParser Base implementation.

This is a base implementation of the powerpc-apple-darwin asm parser dialect.

* Enables infrastructure (essentially isDarwin()) and fixes up the parsing of asm directives to separate out ELF and MachO/Darwin additions.
* Enables parsing of {r,f,v}XX as register identifiers.
* Enables parsing of lo16() hi16() and ha16() as modifiers.

The changes to the test case are from David Fang (fangism).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197324 91177308-0d34-0410-b5e6-96231b3b80d8
Don't manually calculate size in bytes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197327 91177308-0d34-0410-b5e6-96231b3b80d8
[Stackmap] Refactor operand parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197329 91177308-0d34-0410-b5e6-96231b3b80d8
Replace string matching with a switch on Triple::getEnvironment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197332 91177308-0d34-0410-b5e6-96231b3b80d8
Fix AsmWriter's handling of SPIR calling conventions. Patch by Boaz Ouriel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197335 91177308-0d34-0410-b5e6-96231b3b80d8
Ensure bitcode encoding of global variable attributes stays stable. Patch by Boaz Ouriel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197340 91177308-0d34-0410-b5e6-96231b3b80d8
There is no exp10 on NetBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197348 91177308-0d34-0410-b5e6-96231b3b80d8
Last change for mips16 prolog/epilog cleanup and optimization.
Some tiny cosmetic code changes to follow. Because of the wide
ranging nature of the patch a full 24 test cycle was needed to
check against regression. This was the smallest patch I could
make to progress from the earlier ones in the series. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197350 91177308-0d34-0410-b5e6-96231b3b80d8
Get rid of an superfluous tab in the .s file. This was originally
part of a multi-line pseudo which worked around a linker bug for mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197356 91177308-0d34-0410-b5e6-96231b3b80d8
Fix some indentation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197357 91177308-0d34-0410-b5e6-96231b3b80d8
remove an uneeded statement (condition is covered by the statement
that follows).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197358 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64]Fix the pattern match failure for v1i8/v1i16/v1i32 types.
Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them.
E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32:
     bitcast (load i32) to v1i32 -> load v1i32.
So this patch fixes such problems for load/dup instructions.
If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197361 91177308-0d34-0410-b5e6-96231b3b80d8
Fix Android regression in r197332.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197366 91177308-0d34-0410-b5e6-96231b3b80d8