* Makefile.in (DRIVER_DEFINES): Use $(if), not $(and).

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203125 138bc75d-0d04-0410-961f-82ee72b054a4
This patch fixes an issue where expansion of an ORIF expression arbitrarily
applied the probability that the entire condition was true to just the 
first condition. When the ORIF true probability was 100%, this resulted
in the second condition's jump being given a count of zero (since the
first condition's jump got 100% of the count), leading to incorrect function
splitting when it had a non-zero probability in reality. Since there
currently isn't better information about which condition resulted
in the ORIF being true, apply a 50-50 probability that it is the first
vs. second condition that caused the entire expression to be true,
so that neither condition's true label ends up as a 0-count bb.

An equivalent fix is made for ANDIF expansion.

2013-10-02  Teresa Johnson  <tejohnson@google.com>

	* dojump.c (do_jump_1): Divide probability between
	both conditions of a TRUTH_ORIF_EXPR.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203126 138bc75d-0d04-0410-961f-82ee72b054a4
compiler: Use backend interface for numeric expressions.

	* go-gcc.cc: Include "real.h" and "realmpfr.h".
	(Backend::integer_constant_expression): New function.
	(Backend::float_constant_expression): New function.
	(Backend::complex_constant_expression): New function.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203127 138bc75d-0d04-0410-961f-82ee72b054a4

	* graphite-scop-detection.c: Include tree-ssa-propagate,h.
	* graphite-sese-to-poly.c: Include tree-ssa-propagate.h.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203129 138bc75d-0d04-0410-961f-82ee72b054a4
	* Makefile.in (expmed.o-warn): Remove.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203130 138bc75d-0d04-0410-961f-82ee72b054a4
	PR libstdc++/58594
	* include/bits/shared_ptr_base.h
	(_Sp_counted_ptr_inplace::_M_get_deleter()): Cast away cv-quals.
	* testsuite/20_util/shared_ptr/creation/58594.cc: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203131 138bc75d-0d04-0410-961f-82ee72b054a4
2013-10-02  Jonathan Wakely  <jwakely.gcc@gmail.com>
	    Daniel Krugler  <daniel.kruegler@gmail.com>

	PR libstdc++/58569
	* include/std/functional (function::_CheckResult): Move to namespace
	scope and rename to __check_func_return_type.
	* testsuite/20_util/function/58569.cc: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203132 138bc75d-0d04-0410-961f-82ee72b054a4
2013-10-02  Tobias Burnus  <burnus@net-b.de>

        PR fortran/58593
        * trans-expr.c (gfc_conv_string_tmp): Fix obtaining
        the byte size of a single character.

2013-10-02  Tobias Burnus  <burnus@net-b.de>

        PR fortran/58593
        * gfortran.dg/char_length_19.f90: New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203135 138bc75d-0d04-0410-961f-82ee72b054a4
	* config/x-linux (host-linux.o): Remove header dependencies.
	Use $(COMPILE) and $(POSTCOMPILE).
	* config/t-linux-android (linux-android.o): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203136 138bc75d-0d04-0410-961f-82ee72b054a4
runtime: Fix append of slice with elements of zero size.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203140 138bc75d-0d04-0410-961f-82ee72b054a4
2013-10-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/58587
	* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off
	setting -mvsx-timode by default until the underlying problem is
	fixed.
	(RS6000_CPU, power7 defaults): Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203142 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203146 138bc75d-0d04-0410-961f-82ee72b054a4
2013-10-02  Vladimir Makarov  <vmakarov@redhat.com>

	* lra-constraints.c (process_alt_operand): Calculate scratch_p and
	use it.  Use smaller increase for scratch.  Don't increase reject
	for early clobber scratch.
	* lra-eliminations.c (eliminate_regs_in_insn): Remove all insns
	setting eliminated regs except setting fp from hfp.
	(lra_eliminate): Check lra_insn_recog_data on NULL.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203147 138bc75d-0d04-0410-961f-82ee72b054a4
	* config.gcc (hppa*64*-*-linux*): Don't add pa/t-linux to tmake_file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203148 138bc75d-0d04-0410-961f-82ee72b054a4
	* config.host (hppa*64*-*-linux*): Define extra_parts.
	(hppa*-*-linux*): Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203151 138bc75d-0d04-0410-961f-82ee72b054a4
2013-10-02  Teresa Johnson  <tejohnson@google.com>

	* predict.c (probably_never_executed): New function.
	(probably_never_executed_bb_p): Invoke probably_never_executed.
	(probably_never_executed_edge_p): Ditto.
	* bb-reorder.c (find_rarely_executed_basic_blocks_and_crossing_edges):
	Treat profile insanities conservatively.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203152 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Remove un-necessary secondary reload for addition to SP.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203156 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Fix PR58460

PR58460, the add and sub shifted register instruction forms in AArch64
do not permit the stack register.  This patch removes k constraint
from the relevant patterns and adds reduced form of the test case.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203157 138bc75d-0d04-0410-961f-82ee72b054a4
[gcc/]
2013-10-03  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            Richard Earnshaw  <richard.earnshaw@arm.com>

	* config/arm/aarch-common-protos.h (struct alu_cost_table): New.
	(struct mult_cost_table): Likewise.
	(struct mem_cost_table): Likewise.
	(struct fp_cost_table): Likewise.
	(struct vector_cost_table): Likewise.
	(cpu_cost_table): Likewise.
	* config/arm/arm.opt (mold-rts-costs): New option.
	(mnew-generic-costs): Likewise.
	* config/arm/arm.c (generic_extra_costs): New table.
	(cortexa15_extra_costs): Likewise.
	(arm_slowmul_tune): Use NULL as new costs.
	(arm_fastmul_tune): Likewise.
	(arm_strongarm_tune): Likewise.
	(arm_xscale_tune): Likewise.
	(arm_9e_tune): Likewise.
	(arm_v6t2_tune): Likewise.
	(arm_cortex_a5_tune): Likewise.
	(arm_cortex_a9_tune): Likewise.
	(arm_v6m_tune): Likewise.
	(arm_fa726te_tune): Likewise.
	(arm_cortex_a15_tune): Use cortex15_extra_costs.
	(arm_cortex_tune): Use generict_extra_costs.
	(shifter_op_p): New function.
	(arm_unspec_cost): Likewise.
	(LIBCALL_COST): Define.
	(arm_new_rtx_costs): New function.
	(arm_rtx_costs): Use arm_new_rtx_costs when core-specific
	table is available. Use old costs otherwise unless mnew-generic-costs
	is specified.
	* config/arm/arm-protos.h (tune_params): Add insn_extra_cost field.
	(cpu_cost_table): Declare.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203160 138bc75d-0d04-0410-961f-82ee72b054a4
[gcc]
2013-10-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,
	ceildf2, btruncdf2, instead of vsx_* name.

	* config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic
	iterators to only do V2DF and V4SF here.  Move the DF code to
	rs6000.md where it is combined with SF mode.  Replace <VSv> with
	just 'v' since only vector operations are handled with these insns
	after moving the DF support to rs6000.md.
	(vsx_sub<mode>3): Likewise.
	(vsx_mul<mode>3): Likewise.
	(vsx_div<mode>3): Likewise.
	(vsx_fre<mode>2): Likewise.
	(vsx_neg<mode>2): Likewise.
	(vsx_abs<mode>2): Likewise.
	(vsx_nabs<mode>2): Likewise.
	(vsx_smax<mode>3): Likewise.
	(vsx_smin<mode>3): Likewise.
	(vsx_sqrt<mode>2): Likewise.
	(vsx_rsqrte<mode>2): Likewise.
	(vsx_fms<mode>4): Likewise.
	(vsx_nfma<mode>4): Likewise.
	(vsx_copysign<mode>3): Likewise.
	(vsx_btrunc<mode>2): Likewise.
	(vsx_floor<mode>2): Likewise.
	(vsx_ceil<mode>2): Likewise.
	(vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.
	(vsx_sminsf3): Likewise.
	(vsx_fmadf4): Likewise.
	(vsx_fmsdf4): Likewise.
	(vsx_nfmadf4): Likewise.
	(vsx_nfmsdf4): Likewise.
	(vsx_cmpdf_internal1): Likewise.

	* config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it
	simpler to select whether a target has SPE or traditional floating
	point support in iterators.
	(TARGET_DF_SPE): Likewise.
	(TARGET_SF_FPR): Likewise.
	(TARGET_DF_FPR): Likewise.
	(TARGET_SF_INSN): Macros to say whether floating point support
	exists for a given operation for expanders.
	(TARGET_DF_INSN): Likewise.

	* config/rs6000/rs6000.c (Ftrad): New mode attributes to allow
	combining of SF/DF mode operations, using both traditional and VSX
	registers.
	(Fvsx): Likewise.
	(Ff): Likewise.
	(Fv): Likewise.
	(Fs): Likewise.
	(Ffre): Likewise.
	(FFRE): Likewise.
	(abs<mode>2): Combine SF/DF modes using traditional floating point
	instructions.  Add support for using the upper DF registers with
	VSX support, and SF registers with power8-vector support.  Update
	expanders for operations supported by both the SPE and traditional
	floating point units.
	(abs<mode>2_fpr): Likewise.
	(nabs<mode>2): Likewise.
	(nabs<mode>2_fpr): Likewise.
	(neg<mode>2): Likewise.
	(neg<mode>2_fpr): Likewise.
	(add<mode>3): Likewise.
	(add<mode>3_fpr): Likewise.
	(sub<mode>3): Likewise.
	(sub<mode>3_fpr): Likewise.
	(mul<mode>3): Likewise.
	(mul<mode>3_fpr): Likewise.
	(div<mode>3): Likewise.
	(div<mode>3_fpr): Likewise.
	(sqrt<mode>3): Likewise.
	(sqrt<mode>3_fpr): Likewise.
	(fre<Fs>): Likewise.
	(rsqrt<mode>2): Likewise.
	(cmp<mode>_fpr): Likewise.
	(smax<mode>3): Likewise.
	(smin<mode>3): Likewise.
	(smax<mode>3_vsx): Likewise.
	(smin<mode>3_vsx): Likewise.
	(negsf2): Delete SF operations that are merged with DF.
	(abssf2): Likewise.
	(addsf3): Likewise.
	(subsf3): Likewise.
	(mulsf3): Likewise.
	(divsf3): Likewise.
	(fres): Likewise.
	(fmasf4_fpr): Likewise.
	(fmssf4_fpr): Likewise.
	(nfmasf4_fpr): Likewise.
	(nfmssf4_fpr): Likewise.
	(sqrtsf2): Likewise.
	(rsqrtsf_internal1): Likewise.
	(smaxsf3): Likewise.
	(sminsf3): Likewise.
	(cmpsf_internal1): Likewise.
	(copysign<mode>3_fcpsgn): Add VSX/power8-vector support.
	(negdf2): Delete DF operations that are merged with SF.
	(absdf2): Likewise.
	(nabsdf2): Likewise.
	(adddf3): Likewise.
	(subdf3): Likewise.
	(muldf3): Likewise.
	(divdf3): Likewise.
	(fred): Likewise.
	(rsqrtdf_internal1): Likewise.
	(fmadf4_fpr): Likewise.
	(fmsdf4_fpr): Likewise.
	(nfmadf4_fpr): Likewise.
	(nfmsdf4_fpr): Likewise.
	(sqrtdf2): Likewise.
	(smaxdf3): Likewise.
	(smindf3): Likewise.
	(cmpdf_internal1): Likewise.
	(lrint<mode>di2): Use TARGET_<MODE>_FPR macro.
	(btrunc<mode>2): Delete separate expander, and combine with the
	insn and add VSX instruction support.  Use TARGET_<MODE>_FPR.
	(btrunc<mode>2_fpr): Likewise.
	(ceil<mode>2): Likewise.
	(ceil<mode>2_fpr): Likewise.
	(floor<mode>2): Likewise.
	(floor<mode>2_fpr): Likewise.
	(fma<mode>4_fpr): Combine SF and DF fused multiply/add support.
	Add support for using the upper registers with VSX and
	power8-vector.  Move insns to be closer to the define_expands. On
	VSX systems, prefer the traditional form of FMA over the VSX
	version, since the traditional form allows the target not to
	overlap with the inputs.
	(fms<mode>4_fpr): Likewise.
	(nfma<mode>4_fpr): Likewise.
	(nfms<mode>4_fpr): Likewise.

[gcc/testsuite]
2013-10-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p8vector-fp.c: New test for floating point
	scalar operations when using -mupper-regs-sf and -mupper-regs-df.
	* gcc.target/powerpc/ppc-target-1.c: Update tests to allow either
	VSX scalar operations or the traditional floating point form of
	the instruction.
	* gcc.target/powerpc/ppc-target-2.c: Likewise.
	* gcc.target/powerpc/recip-3.c: Likewise.
	* gcc.target/powerpc/recip-5.c: Likewise.
	* gcc.target/powerpc/pr72747.c: Likewise.
	* gcc.target/powerpc/vsx-builtin-3.c: Likewise.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203162 138bc75d-0d04-0410-961f-82ee72b054a4