Make the fields in the diagram match the descriptive text above them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177314 91177308-0d34-0410-b5e6-96231b3b80d8
Include '.test' suffix in target specific lit configs that need it

Apparently my final cleanup to use a relevant suffix for these tests before
committing r176831 caused them to stop running since lit wasn't configured to
run tests with that suffix in those directories (why don't we just have a
global suffix list?). So, add the suffix to the relevant directories & fix the
test that has bitrotted over the last week due to my debug info schema changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177315 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen fix for the new machine model.

Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
Check whether a pointer is non-null (isKnownNonNull) in isKnownNonZero.

This handles the case where we have an inbounds GEP with alloca as the pointer.
This fixes the regression in PR12750 and rdar://13286434.
Note that we can also fix this by handling some GEP cases in isKnownNonNull.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177321 91177308-0d34-0410-b5e6-96231b3b80d8
Annotate X86 arithmetic instructions with SchedRW lists.

This new-style scheduling information is going to replace the
instruction iteneraries.

This also serves as a test case for Andy's fix in r177317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323 91177308-0d34-0410-b5e6-96231b3b80d8
Add SchedRW annotations to most of X86InstrSSE.td.

We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary leading comment characters in lit-only file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327 91177308-0d34-0410-b5e6-96231b3b80d8
Change test cases to handle unaligned references.

Hal Finkel recently added code to allow unaligned memory references
for PowerPC.  Two tests were temporarily modified with
-disable-ppc-unaligned to keep them from failing.  This patch adjusts
the expected code generation for the unaligned references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177328 91177308-0d34-0410-b5e6-96231b3b80d8
Extend global merge pass to optionally consider global constant variables.
Also add some checks to not merge globals used within landing pad instructions or marked as "used".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331 91177308-0d34-0410-b5e6-96231b3b80d8
ARM cost model: Correct cost for some cheap float to integer conversions

Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
  cost of 16 for instruction:   %r = fptoui <4 x float> %v0 to <4 x i16>

While we would emit:
  vcvt.s32.f32  q8, q8
  vmovn.i32 d16, q8
  vuzp.8  d16, d17

All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.

radar://13434072

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177333 91177308-0d34-0410-b5e6-96231b3b80d8
ARM cost model: Make some vector integer to float casts cheaper

The default logic marks them as too expensive.

For example, before this patch we estimated:
  cost of 16 for instruction:   %r = uitofp <4 x i16> %v0 to <4 x float>

While this translates to:
  vmovl.u16 q8, d16
  vcvt.f32.u32  q8, q8

All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.

radar://13445992

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177334 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PPC unaligned 64-bit loads and stores

PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.

In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
Remove trailing spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177339 91177308-0d34-0410-b5e6-96231b3b80d8
Register the flush function for each compile unit.

For each compile unit, we want to register a function that will flush that
compile unit. Otherwise, __gcov_flush() would only flush the counters within the
current compile unit, and not any outside of it.

PR15191 & <rdar://problem/13167507>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177340 91177308-0d34-0410-b5e6-96231b3b80d8
Change NULL to 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177342 91177308-0d34-0410-b5e6-96231b3b80d8
[ms-inline asm] Avoid emitting a redundant sizing directive, if we've already
parsed one.  Test case coming shortly.
rdar://13446980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177347 91177308-0d34-0410-b5e6-96231b3b80d8
Make method private. Keep coding standard.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177348 91177308-0d34-0410-b5e6-96231b3b80d8
Make methods const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177350 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unneeded #includes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177351 91177308-0d34-0410-b5e6-96231b3b80d8
Add some constantness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356 91177308-0d34-0410-b5e6-96231b3b80d8