[FEATURE] Add simplex DPRAM library component

The simplex DPRAM component provides one write and one read port.

Change-Id: I1f798d5690cedbd99f826509dde035ec9df85733
Reviewed-on: http://brateggevoat1/gerrit/1423
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add host interface documentation

- Add doxygen documentation for source files.
- Add wavedrom waves
- Add scripts to generate documentation

Change-Id: I3eded64181bbd78af4823a9fc3af5a11e1adadd1
Reviewed-on: http://brateggevoat1/gerrit/1418
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix architecture selection of SPI slave entity

This fix prevents errors in Qsys designs using POWERLINK IP-Core together
with SPI bridge.
- PDI SPI is fixed to synchronous clock architecture
- SPI bridge is fixed to asynchronous clock architecture

Change-Id: Ib9887c3cf81230a51cc797fd5b968410e61b5581
Reviewed-on: http://brateggevoat1/gerrit/1434
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Revise release scripts

- Remove release directory cleanup
- Add parameter to set release target directory

Change-Id: Ibc9c579159a4d5aff2c98daac05a62ef052503f1
Reviewed-on: http://brateggevoat1/gerrit/1437
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Enable modelsim synthesis check

This enables the synthesis checker included in modelsim.

Change-Id: I2610c0d6280cc80bbbc0de50c783d098e6d480e9
Reviewed-on: http://brateggevoat1/gerrit/1439
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add global constants for true and false

Change-Id: Iec26a57326109c4c3e279fb943d355aaa2e8ca7f
Reviewed-on: http://brateggevoat1/gerrit/1440
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Add missing port assignment in triple buffer DPRAM

Add missing iEnable assignment to DPRAM instantiation.

Change-Id: I30238bb72b09dc8615464be5e925514fb93b2d6f
Reviewed-on: http://brateggevoat1/gerrit/1444
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix simulation script

- Return exit code to caller.
- Reverted quiet mode to see all prints.

Change-Id: I3aaa33a3e0bd363c11cf35526a4b83509ab3df09
Reviewed-on: http://brateggevoat1/gerrit/1443
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix DPRAM model read output

Assign readdata after shared variable is set to the new value. This
ensures that in the next clock cycle the new data is available.

Change-Id: I58fb5192ab8ffe7055a674be8fdea92b3a0f890a
Reviewed-on: http://brateggevoat1/gerrit/1442
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
Merge branch 'task-axi4_lite_wrapper_Joerg' into task-axi4_lite_wrapper
[TASK] host parameters are moved to hostiflib-mem.h