SCEV: Make the final add of an inbounds GEP nuw if we know that the index is positive.

We can't do this for the general case as saying a GEP with a negative index
doesn't have unsigned wrap isn't valid for negative indices.
  %gep = getelementptr inbounds i32* %p, i64 -1

But an inbounds GEP cannot run past the end of address space. So we check for
the very common case of a positive index and make GEPs derived from that NUW.
Together with Andy's recent non-unit stride work this lets us analyze loops
like

  void foo3(int *a, int *b) {
    for (; a < b; a++) {}
  }

PR12375, PR12376.

Differential Revision: http://llvm-reviews.chandlerc.com/D2033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193514 91177308-0d34-0410-b5e6-96231b3b80d8
lit: multiprocessing platform fix attempt

The error raised by Python varies by platform(!), so let's just catch any
exception and fall back.

Thanks to Sylvestre Ledru for noticing this on a Debian / Python 2.7 system
running code coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193516 91177308-0d34-0410-b5e6-96231b3b80d8
Keep TBAA info when rewriting SelectionDAG loads and stores

Most SelectionDAG code drops the TBAA info when creating a new form of a
load and store (e.g. during legalization, or when converting a plain
load to an extending one).  This patch tries to catch all cases where
the TBAA information can legitimately be carried over.

The patch adds alternative forms of getLoad() and getExtLoad() that take
a MachineMemOperand instead of individual fields.  (The corresponding
getTruncStore() already exists.)  The idea is to use the MachineMemOperand
forms when all fields are carried over (size, pointer info, isVolatile,
isNonTemporal, alignment and TBAA info).  If some adjustment is being
made, e.g. to narrow the load, then we still pass the individual fields
but also pass the TBAA info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193517 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Respect volatility when checking for aliases

Making useAA() default to true for SystemZ showed that the combiner alias
analysis wasn't handling volatile accesses.  This hit many of the SystemZ
tests, but I arbitrarily picked one for the purpose of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193518 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Set usaAA to true

useAA significantly improves the handling of vector code that has TBAA
information attached.  It also helps other cases, as shown by the testsuite
changes here.  The only real downside I've seen is that it interferes with
MergeConsecutiveStores.  The problem is that that optimization works top
down, starting at the first store in the chain, and looks for cases where
the chain result is only used by a single related store.  These related
stores don't alias, so useAA will have rewritten all the later stores to
use a different chain input (typically the same one as the first store).

I think the advantages outweigh the disadvantages though, so for now I've
just disabled alias analysis for the unaligned-01.ll test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193521 91177308-0d34-0410-b5e6-96231b3b80d8
simplify ConstantRange::getSetSize()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193523 91177308-0d34-0410-b5e6-96231b3b80d8
[arm] Implement eabi_attribute, cpu, and fpu directives.

This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.

These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193525 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: Refactor DAG patterns to enable parsing one pattern at a time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193526 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen: remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193527 91177308-0d34-0410-b5e6-96231b3b80d8
Convert a llc -filetype=obj test into a llvm-mc test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193534 91177308-0d34-0410-b5e6-96231b3b80d8
Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.

When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.

Fixes <rdar://problem/15155975>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
Convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193536 91177308-0d34-0410-b5e6-96231b3b80d8
Convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193537 91177308-0d34-0410-b5e6-96231b3b80d8
Convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193538 91177308-0d34-0410-b5e6-96231b3b80d8
Convert another llc -filetype=obj test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193539 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Simplify LowerFormalArguments using getRegClassFor.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193540 91177308-0d34-0410-b5e6-96231b3b80d8
Remove 2.4 from the list of supported Python versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193541 91177308-0d34-0410-b5e6-96231b3b80d8
Use the correct reference. Spotted by Sean Silva.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193542 91177308-0d34-0410-b5e6-96231b3b80d8
Remove stray '_'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193543 91177308-0d34-0410-b5e6-96231b3b80d8