Add support for -mavx and -mavx2 flags.
Add Cmm support for 256-bit-wide values.
Add support for 256-bit-wide vectors.
Set LLVM option -stack-alignment=32 when compiling AVX instructions.
Fixup stack spills when generating AVX instructions.

LLVM uses aligned AVX moves to spill values onto the stack, which requires
32-bye aligned stacks. Since the stack in only 16-byte aligned, LLVM inserts
extra instructions that munge the stack pointer. This is very very bad for the
GHC calling convention, so we tell LLVM to assume the stack is 32-byte
aligned. This patch rewrites the spill instructions that LLVM generates so they
do not require an aligned stack.
Pass 256-bit-wide vectors in registers.
Add 256-bit-wide SIMD primitives.
Add support for -mavx512* flags.
Add Cmm support for 512-bit-wide values.
Add support for 512-bit-wide vectors.
Pass 512-bit-wide vectors in registers.
Add 512-bit-wide SIMD primitives.
By default, only pass 128-bit SIMD vectors in registers on X86-64.

LLVM's GHC calling convention only allows 128-bit SIMD vectors to be passed in
machine registers on X86-64. This may change in LLVM 3.4; the hidden flag
-fllvm-pass-vectors-in-regs causes all SIMD vector widths to be passed in
registers on both X86-64 and on X86-32.
Enable -msse to be specified by itself.

This sets the SSE "version" to 1.0.
Check that SIMD vector instructions are compatible with current set of dynamic flags.

SIMD vector instructions currently require the LLVM back-end. The set of
available instructions also depends on the set of architecture flags specified
on the command line.