R600: Fix assembly name for SETGT_INT
R600: Add tests for unsupported condition codes.

All of the le and lt variants are unsupported.
R600: Add support for SET*_DX10 instructions

These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.
R600: Consolidate sub register indices.

Use sub0-15 everywhere.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
R600/SI: Add basic support for more integer vector types.

v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
R600/SI: Make sample intrinsic address parameter type overloaded.

Handle vectors of 1 to 16 integers.

Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
R600/SI: Use proper instructions for array/shadow samplers.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Tablegen: Revert change that added check for SubRegIndex limit

This was accidently committed in
c0f988d7b83f54d87db0ec4052cf06727ff96193
R600: Add an explicit default processor

This is for the case when no processor is passed to the backend.  This
prevents the

'' is not a recognized processor for this target (ignoring processor)

warning from being generated by clang.
R600: Fix 64-bit defines

This fixes indirect addressing on 32-bit systems.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
R600/SI: Add pattern for flog2.

22 more little piglits with radeonsi.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600/SI: add proper 64bit immediate support v2

v2: rebased on current upstream

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600/SI: simplify and fix SMRD encoding

The _SGPR variants where wrong.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600/SI: Add pattern for mul.

20 more little piglits with radeonsi.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600/SI: Handle VGPR64 destination in copyPhysReg().

Allows nexuiz to run with radeonsi.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600/SI: cleanup VGPR encoding

Remove all the unused code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
R600: fix PHI value adding in the structurizer

Otherwise we sometimes produce invalid code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
R600: fix loop analyses in the structurizer

Intersecting loop handling was wrong.

Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
R600: rework flow creation in the structurizer v2

This fixes a couple of bugs and incorrect assumptions,
in total four more piglit tests now pass.

v2: fix small bug in the dominator updating

Signed-off-by: Christian König <christian.koenig@amd.com>
Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8