Create a copy of trunk r2567 to hold work on adding direct support
for conditional loads and stores to IR ("COnditional MEMory")



git-svn-id: svn://svn.valgrind.org/vex/COMEM@2568 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Move this directory to the right place.  Duh.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2569 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add IR level definitions and associated iropt hackery, to support
direct representation of conditional (guarded) loads and stores in IR.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2570 8f6e269a-dfd6-0310-a8e1-e2731360e62c
ARM back end changes, to support code generation for IR guarded loads
and stores.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2571 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Initial front changes for ARM, to generate direct IR for at least some
conditional loads and stores.  Very incomplete -- most load-store
cases still use the old scheme.



git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2572 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Make a couple more load/store cases use IRLoadG/IRStoreG.  Also add
debug printing to find out which load/store cases are most used in
practice.



git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2573 8f6e269a-dfd6-0310-a8e1-e2731360e62c
* make ARM word and unsigned byte load/stores use LoadG/StoreG
* correctness fix for default cases in already-done cases


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2574 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Change a bunch more Thumb load/store events to use IR guarded loads/stores.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2589 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove a bit of debug printing.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2593 8f6e269a-dfd6-0310-a8e1-e2731360e62c
IR: add the ability to specify the call-didn't-happen ("default")
return value for conditional dirty helper calls returning values.  The
default value can be either all-zeroes or all-ones.



git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2594 8f6e269a-dfd6-0310-a8e1-e2731360e62c
ARM back end: handle IRDefaults in dirty helper calls.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2595 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Hook up a couple of ARM (encoded) load/store cases to the new guarded
load/store IR stuff.  I think these are the last I am going to do, for
now.


git-svn-id: svn://svn.valgrind.org/vex/branches/COMEM@2599 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge, from branches/COMEM, revisions 2568 to 2641.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2642 8f6e269a-dfd6-0310-a8e1-e2731360e62c