fpga: zynq: Correct fpga load when buf is not aligned

When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.

A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.

Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
sf: Merge quad, dual stacked and dual parallel changes

Merged the quad, dual stacked and dual parallel
changes into the new spi framework of v2013.10.

Tested the changes on zc702, zc706. Also, tested on zc706
with Micron device as well.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynqpl: Added devcfg driver for decryption

Added devcfg driver for decryption of the encrypted
image.The driver decrypts the image and loads it
back to DDR.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
image: Added RSA support for zynq

Added RSA support for zynq. This uses the
montogomery multiplications while verifying
the authenticated image.
Modified Makefile to compile rsa-verify.c if
CONFIG_CMD_ZYNQ_RSA was enabled to get rid of
unrequired FDT functionality incase of zynq.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: efuse: Added efuse status register base address

Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: rsa: Added RSA-AES support for zynq

Added the RSA-AES support for zynq.This
verifies authenticated images using rsa2048
and decrypts the encrypted image.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: rsa: Added RSA-AES for the zynq board

Added RSA-AES support for the zynq boards with
config rsa as config option.Added autoboot support
if built for zynq with config rsa config option.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>