refactor and simplify Mem

- Move logic from Verilog backend into Mem
- Express sequential read ports by registering address, not output data
  (this simplifies the implementation, as the read address is known at
  port instantiation time)
- For C++ backend, Randomize sequential read data if same address was
  written on same cycle.  This makes behavior more closely match real
  RAMs.
update manual section on seqRead Mems
make Mem wmask optional; rename to mask

Synopsys DC does a crappy job optimizing out an all-hot write mask;
if the write mask is known to be all-hot, it should be omitted entirely.