Basic beta state mockup.
A few tests to hash out testing areas.
Ignoring rust build files.
Processor can be reset.
PC increments.
Ignoring vim temp files.
Memory as a separate entity.
Memory can be read byte-wise or word-wise.
Opcode decoding.
Instruction decoding made more flexible through macro. Same code can now be used in disassembler.
ADD instruction implemented as template for other instructions.
Abstracted instruction implementations in the form of putting the result of an operation on two registers into a destination register.
Implemented addc, and, andc, and beq.
Implemented bne, cmpeq, cmpeqc, cmple, cmplec, cmplt, cmpltc, div, and divc.
Implemented jmp.
Fixed sign extension bug.
Implemented ld and ldr.
Implemented mul, mulc, or, orc, shl, shlc, shr, shrc, sra, srac, sub, and subc.
Implemented st, xor, xorc, xnor, and xnorc.
Added assembler test code from bsim (6.004 Beta tool).