Added gitignore
Added project vhdl files
Added mandelcore using vhdl 2008 libs
Added memory controller state machine.  Primary operation is 4 word
burst mode which has a variable latency as indicated by a wait line from
the ram chip.  VGA changed to 640x480@60hz mode, pixel clk divided down
accordingly.  Ram controller beginning to be incorporated into testing,
need to pull in an output UART to see memory data pop out of the device.
Merge branch 'master' of github.com:captaincool/mandelHW