EHCI: HSIC: Implement new reset sequence to workaround PHY lockup issue

commit 8e6edcb (usb: ehci: Avoid phy lockup due to SOFs during port
reset) implements a workaround for PHY lockup issue during port reset.
The workaround relies on a hardware debug feature which allows driving
strobe and data lines to reset using ULPI interface.  This is not
working some times for unknown reason.

This patch implements a new reset sequence to workaround the PHY lockup
issue.  The controller drive reset signaling for ~50 msec when reset bit
is set in PORTSC register.  The controller automatically clears this bit
after finishing the reset signaling.  The software can also finish the
reset signaling any time by clearing the reset bit.

According to USB2 spec, Host controller should drive reset signaling for
50 msec for root hub ports.  But HSIC spec allows shorter reset signaling
time (20 msec).  Clear the reset bit in PORTSC register after 20 msec and
start controller immediately to send SOF.  Use controller internal timers
to achieve this.  If reset bit is not cleared in time, perform the sequence
in a loop with interrupts disabled.

CRs-Fixed: 445659
Change-Id: I884cfcd8a53b111bc9434e47ef483dde64fcc1ed
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>

Conflicts:

	include/linux/usb/hcd.h