power: smb349: Enable OTG support

Addition of OTG support in smb349 charger driver

Change-Id: Ib38c9f4c06285ae07d93cfa3c6f5e1637aaa9460
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/86936
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
crypto: tegra-aes: fix "syntax error" in license

Should have been "GPL v2", not "GPLv2".

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Change-Id: I7b4669c023c48e1080de7f87ed7166dc9b47884a
Reviewed-on: http://git-master/r/88101
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: fix compilation with binutils >= 2.21

Fix "Error: .size expression does not evaluate to a constant" with
binutils since version >= 2.21 due to wrong naming of the label
reference.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Change-Id: I3d09c423f993aa5ec8cdf166199774a7a1b18396
Reviewed-on: http://git-master/r/88102
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
tegra: pcie: Fix individual port detection on T20

This commit fix two issues.
1. MMIO space should be reserved for T30 as well
2. There is a bug in link reset sequence causing
   problem in detecting the other slot as well
   on T20

bug 826956
bug 637871

Reviewed-on: http://git-master/r/66814
(cherry picked from commit 11ce98902d0687646eb30a4bd1f9a1d5e8da34ce)

Change-Id: I1843e3a1d897a36768b05b33ab7624889191d011
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/86134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: Clean kernel and I/O mappings upon LP2

There is no need to flush the complete L2 upon LP2
entry but it is necessary to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.

Bug 931316

Change-Id: Ice353f16d35ee24d4387e7b9b135f205c4d0ba32
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/86293
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: host: make nvhost_get_host inline

- nvhost_get_host returns host1x's master driver's
private data
- this host1x master is parent for all its modules.
however, it does not have a parent of its own
- so the debug_not_idle causes crash when there is an
outstanding reference count on host1x by some module
during suspend sequence
- with this change, debug_not_idle returns error to
pm core if host1x has an outstanding ref count. pm core
then safely aborts the suspend and does resume

Bug 947617

Change-Id: Ia2479c192bdd94028d090168f689823658062fd4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/87658
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
video: tegra: host: Set 3D pg timeout to 250ms

Power gating timeout for 3D is too short, and causes oscillation
in non-idle use cases. Increase timeout to 250ms to get more benefits
from power gating.

Bug 914785

Change-Id: I4e37fda260ceecc2fe3e21989789105b7c8fcf36
Reviewed-on: http://git-master/r/87659
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
ARM: mm: Implement complete debug arch v7 save/restore

Implement the complete debug arch v7 save/restore sequence
as required by the ARM Architectural Reference Manual.

Change-Id: Ia346a87b16e759ae5dbbbd02e77eda1e6d6deb82
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/87865
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
video: tegra: host: convert kzalloc to vzalloc

nvhost_job uses kzalloc to hold meta data. Convert
it to vzalloc to avoid large physically contiguous
allocations at runtime.

Change-Id: I13d7e7d60e93354fcf69e5478437fa206b880dcc
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/87967
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
gpio: gpiolib: Support for open drain/collector gpios

Adding support for the open drain gpio on which client
can specify the open drain property through GPIO flag
GPIOF_OPEN_DRAIN at the time of gpio request.
The open drain pins are normally pulled high and it
cannot be driven to output with value of 1 and so
when client request for setting the pin to HIGH, the
gpio will be set to input direction to make pin in tristate
and hence PULL-UP on pins will make the state to HIGH.
The open drain pin can be driven to LOW by setting output
with value of 0.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Cherry-picked from mainline
	aca5ce14eb773a75e5d935968b2e390dc5bd29c3

Change-Id: I097caebcc7cf6fb1497bb0395320dfc061bb6277
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/88264
gpio: gpiolib: Support for open source/emitter gpios

Adding support for the open source gpio on which client
can specify the open source property through GPIO flag
GPIOF_OPEN_SOURCE at the time of gpio request.
The open source pins are normally pulled low and it
cannot be driven to output with value of 0 and so
when client request for setting the pin to LOW, the
gpio will be set to input direction to make pin in tristate
and hence PULL-DOWN on pins will make the state to LOW.
The open source pin can be driven to HIGH by setting output
with value of 1.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

cherry-picked from mainline commit
	25553ff0756c59b617af6bdd280c94e943164184

Change-Id: I3062a5dec7bf745b624d9a147f79d3830927325b
Reviewed-on: http://git-master/r/88265
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
arm: tegra: kai nfc support

1) configure pinmux
2) create pn544_i2c_platform_data
3) register i2c device info using i2c_register_board_info

Bug 949128

Change-Id: I62c82d338724c4f012ac98d7ec61ec9aae1afae5
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/88288
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
mpu3050: remove warning for unassigned irq

Bug 924470

Change-Id: I55310652512bf87ab5fc83479a18a4c685958884
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/88327
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
smp_twd: make sure timer is stopped before registering it

On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.

The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.

Problem seen on VE (Cortex A5) and Tegra.

Signed-off-by: Marc Zyngier <(address hidden)>
Change-Id: I52695f4f9a5c5e3a8973da7668b3b1352e60a80f
Reviewed-on: http://git-master/r/83085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
arm: tegra: kai: Enable 12.75MHz emc for kai

emc registry entries @ 12.75 MHz for kai

Change-Id: Id68a6368d8f41d537eb52ca3ac8e9b816ee4015f
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/86698
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
video: tegra: dc: Fix the race condition of one-shot work.

Add lock to prevent race condition between cancellation of old delayed
work and schedule of new delayed work.

Bug 936337

Change-Id: I52df82e92279163841546127c72be9879ef810d0
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/86730
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
tegra: arm: kai: Enable emc in kai

emc was not inited for kai in main.

Change-Id: I0562ff8fffdc8a9aa8622925aa18d0d4cedb5567
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/86738
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
regulator: provide missing regulator_ stubs

Change-Id: I8a5329284008c03705273dfa49042fc0e07b4b3d
Signed-off-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-on: http://git-master/r/87068
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: implement DC capabilities ioctl

The returned capabilities bitfield is initially 0 (no caps).

bug 942631

Change-Id: Ia7496981e525526147ecebe67b09dc877d3e0c17
Reviewed-on: http://git-master/r/87088
Tested-by: Adam Cheney <acheney@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
ARM: tegra: power: Fix build error on non-SMP systems

Can't use NR_CPUS on non-SMP systems. Just use the maximum.

Change-Id: I00b455adf950869146dfcd176efe4abdbe7aa24e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/87416
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>