PCIe_hdl: Move PCIe files pt.2 - simulation support.
Add support for simulating standalone PCIe firmware under new project
structure. This involves mostly renaming some signal paths due to
changed hierarchy tree.
pcie_fpga: Add missing CS_N signal to the DDR SDRAM core.
Absence of this signal pin could lead to problems with DDR memory
calibration (in other words: it didn't work).
Also change adressing scheme from BANK_ROW_COLUMN to ROW_BANK_COLUMN.
Theoretically it should give better performance in our use case.
pcie_hdl: Add generic parameter in DDRs module for differentiating
between target devices.
I have enough of this shit. Code gets so messy when trying to make
educated guesses about family that it's not worth the trouble.
Just pass the parameter and generate appropiate code.
Plus, fix DDR core pin connections for Virtex6 version.
pcie_hdl: add missing CS_N signals for DDR cores.
pcie_hdl: Invert DDR core reset signal logic for A7 chips.
hdl/modules/*/wb_acq_core/wbgen/*: sync ddr3 start address with ext_clk
Merge remote-tracking branch 'ohwr/master' into pcie-test

Conflicts:
	hdl/modules/pcie/bpm_pcie_ml605.vhd
hdl/*/pcie/*/ddr_Transact.vhd: fix high fanout on ddr_switch signal
hdl/modules/pcie/*: remove RST_ACT_LOW generic

Now, we have only a high active reset option for the
user
hdl/top/*/dbe_bpm_fmc130m_4ch_pcie/*: add .xcf constraints file

Also, updated Manifest file
top/ml_605/dbe_bpm_fmc130m_4ch_pcie/*.ucf: update .ucf file

Add multcycle constraint between wishbone clock and DDR3
UI clock. Passing from these two clock domains happens
when we want to specify the DDR3 start address of the
acquisition. As, this is only qualified upon assertion
of a strobe signal (synchronous to DDR3 UI clock) we can
relax the constraints fot it.
hdl/top/*/*_pcie/clk_gen.vhd: add regular clock output

Now, we have a regular single-ended clock and a BUFG
clock. Also, add differential termination and disable
low_power mode to IBUFGDS primitive
top/pcie/top_ml605.vhd: add bpm_pcie_pkg header
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/: update top file

- Change clock nomenclature to match clk_gen module
- Narrow acquisition FIFO
- Change chipscope debug signals
hdl/Manifest.py: add pcie files to Manifest file
hdl/top/ml_605/*_pcie/: update chipscope project
modules/*/dbe_wishbone_pkg.vhd: add acquisition core package
modules/*/wb_acq_core.vhd: fix missing ext_clk_i declaration

I forgot to fix this after commit 37ae7b2ff, when the
wbgen files were updated
hdl/top/pcie/top_ml605.vhd: remove component and RST_ACT_LOW generic

Forgot to do that in commit 7315149df8, when RST_ACT_LOW generic
was removed