[FEATURE] Add openMAC Qsys component

Change-Id: I2e4f37f763a9576f1fddc6c9b92b374af73ac6c5
Reviewed-on: http://brateggevoat1/gerrit/1576
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add timing constraint generation to Altera openMAC

The openMAC Qsys component automatically sets the needed timing constraints.

Change-Id: I31561076d925215a96d451eaa22686bd32192e32
Reviewed-on: http://brateggevoat1/gerrit/1577
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Rename Xilinx "library" directory to "components"

Change-Id: Ifc6860be9139d9ba6d0344a4f8f86a9c34b01c09
Reviewed-on: http://brateggevoat1/gerrit/1578
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Add common tcl library to Altera openMAC Qsys component

- Use common tcl files also in Altera openMAC configuration
- Extract frequently used Qsys tcl procedures

Change-Id: Ib4338da01cd014d0bf16a7a4445c4c393fae2c00
Reviewed-on: http://brateggevoat1/gerrit/1579
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add Xilinx openMAC component

- Add axi_openmac
- Refactor ipif master handler
- Refactor clock crossing ipcore
- Add common tcl library

Change-Id: Ifff2dfb70081d2319bff95116f1a8462f693729c
Reviewed-on: http://brateggevoat1/gerrit/1580
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add openmac_cfg.h header file generation

Change-Id: I59d90756552a2848ab0cbd00bd07dbf997da1260
Reviewed-on: http://brateggevoat1/gerrit/1581
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Revise clock Xing testbench

Change-Id: Id19010f67a5b44a64d35744370aefa2cbfcbe732
Reviewed-on: http://brateggevoat1/gerrit/1582
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Slave converter outputs byte addresses

Change-Id: I3b14a4dd7aa0092f53e63cf22120a4e3091e7766
Reviewed-on: http://brateggevoat1/gerrit/1583
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix max and min function of global.vhd

Due to collision with time unit "minutes" the min and also max functions are
renamed to minimum and maximum.

Change-Id: I1a983393d61915a486d234082769272ece01d28a
Reviewed-on: http://brateggevoat1/gerrit/1585
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Add simplex DPRAM implementation for Xilinx platform

Due to weird synthesis results an explicit implementation is used.

Change-Id: Ied476f50d003d4d140cb4c0cdcfffee8f02be7bb
Reviewed-on: http://brateggevoat1/gerrit/1584
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Remove POWERLINK IP-Core

Change-Id: I9e0eeaa66756d1c967706b919c80577d058b57c2
Reviewed-on: http://brateggevoat1/gerrit/1586
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Avoid multiple vhd files after Qsys generation

After Qsys generation the ipcore vhd files are copied to the Quartus
project directory. In order to avoid multiple vhd files with the same
entity/architecture/package/etc a flat path tree is created. Common files
are simply overwritten.

Change-Id: I1d8db6cd098b9a17f4a3d62a82caa083f1eecca3
Reviewed-on: http://brateggevoat1/gerrit/1590
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Sebastian Muelhausen <sebastian.muelhausen@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add QIP file for RMII to MII converter

This enables using the RMII to MII converter ipcore directly in Quartus
designs.

Change-Id: Ibb384976453d25ff3f7beb2626864a63fda912c7
Reviewed-on: http://brateggevoat1/gerrit/1596
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Sebastian Muelhausen <sebastian.muelhausen@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Control visibility of Tx/Rx buffer/burst sizes in AXI openMAC

Change-Id: I120dec8d16fbc6b49d336e5944cfbfa6deb49f2d
Reviewed-on: http://brateggevoat1/gerrit/1602
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Remove debug messages of openMAC Qsys component

Change-Id: I7a2708c2ee689694202770a6389a839900b540b6
Reviewed-on: http://brateggevoat1/gerrit/1601
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>