tcg-ppc64: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Add an LK argument to tcg_out_call

This will enable the generation of tail-calls in a future patch.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Don't load the static chain from TCG

There are no helpers that require the static chain.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Look through the function descriptor when profitable

Loading 32-bit immediates instead of memory will be faster.
Don't attempt to generate full 64-bit immediates.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Tidy register allocation order

Remove conditionalization from tcg_target_reg_alloc_order, relying on
reserved_regs to prevent register allocation that shouldn't happen.
So R11 is now present in reg_alloc_order for __APPLE__, but also now
reserved.

Sort reg_alloc_order into call-saved, call-clobbered, and parameters.
This reduces the effect of values getting spilled and reloaded before
function calls.

Whether or not it is reserved, R2 (TOC) is always call-clobbered.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Create PowerOpcode

This makes some bits easier to debug, being presented with a symbol
instead of a number inside gdb.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Handle long offsets better

Previously we'd only handle 16-bit offsets from memory operand without falling
back to indexed, but it's easy to use ADDIS to handle full 32-bit offsets.

This also lets us unify code that existed inline in tcg_out_op for handling
addition of large constants.

The new R2 temporary was marked reserved for the AIX calling convention, but
the register really is call-clobbered and since tcg generated code has no use
for a TOC, it's available for use.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use indirect jump threading

We were always doing an indirect jump anyway, and the sequence is
never longer than the 6 insns we were reserving for the direct jump.
Futher cleanups will reduce the length of the constant address load.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Setup TCG_REG_TB

A handy value "near" the rest of the program's dynamic allocation.
We'll be able to use this value for constant address generation,
cross-TB references, and in the further future, constant pool refs.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCG_REG_TB in tcg_out_movi and tcg_out_mem_long

This results in significant code size reductions when manipulating
pointers into TCG's own data structures.  E.g.

-OUT: [size=180]
+OUT: [size=132]
...
-xxx:  li      r2,16383			# goto_tb
-xxx:  rldicr  r2,r2,32,31
-xxx:  oris    r2,r2,39128
-xxx:  ori     r2,r2,376
-xxx:  ldx     r30,0,r2
+xxx:  addis   r30,r30,-544
+xxx:  ld      r30,-8(r30)
...
-xxx:  li      r3,16383			# exit_tb
-xxx:  rldicr  r3,r3,32,31
-xxx:  oris    r3,r3,39128
-xxx:  ori     r3,r3,288
+xxx:  addis   r3,r30,-544
+xxx:  addi    r3,r3,-96

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Tidy tcg_target_qemu_prologue

Use the helper macros like TAI.  Fix formatting.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Streamline tcg_out_tlb_read

Less conditional compilation.  Merge an add insn with the indexed
memory load insn.  Load the tlb addend earlier.  Avoid the address
update memory form.

Fix a bug in not allowing large enough tlb offsets for some guests.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATION

Signed-off-by: Richard Henderson <rth@twiddle.net>