[ms-inline asm] Move this logic into a static function as it's only applicable
when parsing MS-style inline assembly.  No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179407 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for additional vector instructions in the interpreter.

patch by Veselov, Yuri <Yuri.Veselov@intel.com>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179409 91177308-0d34-0410-b5e6-96231b3b80d8
Add debug prints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179412 91177308-0d34-0410-b5e6-96231b3b80d8
CostModel: increase the default cost of supported floating point operations from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179413 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: add support for vectorization of diamond shaped trees. We now perform a preliminary traversal of the graph to collect values with multiple users and check where the users came from. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179414 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Check the operand types before merging fcmp ord & fcmp ord.

Fixes PR15737.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179417 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r179409 because it caused some warnings and some of the build bots fail.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179418 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Instruction selection patterns for carry-setting and using add
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r179420 and r179421.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
[ms-inline asm] Simplify the logic by using parsePrimaryExpr.  No functional
change intended.  Test case previously added in r178568.
Part of rdar://13611297

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179425 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Override TargetLoweringBase::isShuffleMaskLegal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179433 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Reapply r179420 and r179421.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
Finish templating MachObjectFile over endianness.

We are now able to handle big endian macho files in llvm-readobject. Thanks to
David Fang for providing the object files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179440 91177308-0d34-0410-b5e6-96231b3b80d8
Some versions of gcc don't like typenames in these places.

Should fix the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179441 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
Add typenames to see if bot goes green.

I hope this brings http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32 back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179446 91177308-0d34-0410-b5e6-96231b3b80d8
Catch another case where SD fails to propagate node order.

I need to handle this for the test case in my following scheduler
commit.

Work is already under way to redesign the mechanism for node order
propagation because this case by case approach is unmaintainable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179448 91177308-0d34-0410-b5e6-96231b3b80d8
MI-Sched: schedule physreg copies.

The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179449 91177308-0d34-0410-b5e6-96231b3b80d8
X86 machine model: reduce SandyBridge and Haswell ILPWindow.

The initial values were arbitrary. I want them to be more
conservative. This represents the number of latency cycles hidden by
OOO execution. In practice, I think it should be within a small factor
of the complex floating point operation latency so the scheduler can
make some attempt to hide latency even for smallish blocks.

These are by no means the best values, just a starting point for
tuning heuristics. Some benchmarks such as TSVC run faster with this
lower value for SandyBridge. I haven't run anything on Haswell, but
it's shouldn't be 2x SB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179450 91177308-0d34-0410-b5e6-96231b3b80d8