mako: msm: hsic: Disallow processor idle sleep while driving resume signal

HSIC controller should send SOF with in 3 msec after completing
the resume signal.  If processor is in idle sleep state, the timer
interrupt generated by HSIC controller to indicate resume completion
gets delayed.  If the interrupt handler is not run with in 3msec
after resume, the resume sequence is repeated.  Disallow processor
idle sleep to avoid multiple resume cycles.

CRs-Fixed: 397154
Change-Id: Ie2c6f60b3a36f46f8246e2e0f41a64675df632a5
Signed-off-by: Iliyan Malchev <malchev@google.com>
mako: EHCI: HSIC: Add support to vote for SVS digital voltage

HSIC HW can operate at SVS digital voltage when it is active.
Currently HSIC is voting for 120Mhz SFAB and 64Mhz DFAB clock
frequencies. Clock frequencies are directly proportional to SVS
voltage. If DFAB is running at 64Mhz or SFAB is running at 120Mhz
or higher SVS is not possible even though HSIC votes for it. Hence
do not vote for SFAB clock frequency and only vote for 32Mhz for
DFAB in order to allow SVS to happen. Voting for SVS voltage reduces
current consumption by 3mA in HSDPA network.

Change-Id: Ic76f0c8346e3387b1647f41f77eb06babbd9a422
Signed-off-by: Iliyan Malchev <malchev@google.com>