ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC

The pincontrol driver for Tegra124 is build through config
PINCTRL_TEGRA124. Select this config option whenever Tegra124
SoC is enabled.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Fix some whitespace oddities

Some of the powergate code uses unusual spacing around == and has a tab
instead of a space before an opening parenthesis.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Rename cpu0 powergate to crail

This matches the name of the powergate as listed in the TRM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Export tegra_powergate_power_off()

This function can be used by drivers, which in turn may be built as
modules. Export the symbol so it is available to modules.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Export tegra_powergate_remove_clamping()

Drivers can use the tegra_powergate_remove_clamping() API during
initialization. In order to allow such drivers to be built as modules,
export the symbol.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ASoC: tegra: update module reset list for Tegra124

Tegra124 adds a number of extra modules into the configlink bus, which
must be taken out of reset before the bus is used. Update the AHUB
driver to know about these extra modules (the AHUB HW module hosts the
configlink bus).

Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@linaro.org>
---
This patch depends on "ASoC: tegra: use reset framework" to compile,
which is ack'd and slated to go through a (large) topic branch in the
Tegra tree. So, we can either:

a) Merge that Tegra topic branch into the ASoC tree, then apply this.
   Note that I haven't created the topic branch yet, since I'm still
   waiting for DMA dependencies to be applied.

b) Apply this change to the Tegra tree too. This change isn't directly
   related to the changes in the Tegra tree; it just makes use of the new
   reset controller feature that's introduced there.
ARM: tegra: add port FF to GPIO IDs

NVIDIA Tegra124 supports has the new GPIO port as GPIO_FF.
Add the macro for this port name.

Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add missing unit addresses to DT

DT node names should include a unit address iff the node has a reg
property. For Tegra DTs at least, we were previously applying a different
rule, namely that node names only needed to include a unit address if it
was required to make the node name unique. Consequently, many unit
addresses are missing. Add them.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: fix node sort order

For Tegra DT files, I've been attempting to keep the nodes sorted in
the order:
1) Nodes with reg, in order of reg.
2) Nodes without reg, alphabetically.

This patch fixes a few escapees that I missed:-(

The diffs look larger than they really are, because sometimes when one
node was moved up or down, diff chose to represent this as many other
nodes being moved the other way!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add clock properties for devices of Tegra124

This patch adds clock properties for devices in the DT for basic support
of Tegra124 SoC.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren, added missing unit address to "clock" node]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add reset properties to Tegra124 DTs

The DT bindings now require module resets to be specified. The earlier
patches which added these nodes were originally written before that
requirement.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: add APB DMA controller to Tegra124 DT

Instantiate the APB DMA controller in the Tegra124 DT, and add all
DMA-related properties to other DT nodes that rely on (reference) the
DMA controller's node.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: add Tegra124 pinmux node to DT

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked by: Laxman Dewangan <ldewangan@nvidia.com>
ARM: tegra: add MMC controllers to Tegra124 DT

Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.

Also enable the relevant controllers in the Venice2 board DT.

power-gpios property suggested by Thierry Reding.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
ARM: tegra: add I2C controllers to Tegra124 DT

Tegra124 has 6 I2C controllers. The first 5 have identical configuration
to Tegra114, but the sixth obviously has different interrupt/... IDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: enable I2C controllers on Venice2

Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add audio-related device to Tegra124 DT

Tegra124 contains a similar set of audio devices to previous Tegra chips.
Specifically, there is an AHUB device which contains DMA FIFOs and audio
routing, and which hosts various audio-related components such as I2S
controllers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add sound card to Venice2 DT

Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Add Tegra124 PWM support

The PWM controller on Tegra124 is the same as the one on earlier SoC
generations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, added reset properties]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Enable PWM on Venice2

Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>