Modifies operand encoding in specification.

This greatly reduces the complexity of the operand encoding,
making the CPU faster and more efficient. Additionally, it provides
a more consistent implementation over the DCPU. The way the DCPU
was implemented was most likely because of its limited 16-bit address
space, along with some legacy crud that accumulated while going
through spec versions. We have the opportunity here to fix those issues.

The new imlpementation makes no distinction between the handling
of the general purpose- and special- registers. They are all equal as far
as the decoder is concerned.
Fixes Cpu and Unit tests to match the changes to the operand
encoding in the specification.
Adds a version number to the specification document.