iInitial commit of some verilog before I fiddle with it
Hamming sidtance calculated using a giant case.
I tried a lookup, but I failed and the internet told me to do it this way.
Add find_iso_from_start mudule
Find_iso_from_start with params and big arrays of regs
 - Doesn't work, replacing with ram blocks (not as easy to parameterise)
Use ram blocks - will be Altera only
Add gitignore for build output