new file:   protocols/MSI_MOSI_inclusive-RnR-L115cache.sm
	new file:   protocols/MSI_MOSI_inclusive-RnR-L2cache.sm
	new file:   protocols/MSI_MOSI_inclusive-RnR-dir.sm
	new file:   protocols/MSI_MOSI_inclusive-RnR-msg.sm
	new file:   protocols/MSI_MOSI_inclusive-RnR.slicc
version limpia
	modified:   ../protocols/MSI_MOSI_inclusive-L2cache.sm
	modified:   ../protocols/MSI_MOSI_inclusive-RnR-L2cache.sm
	new file:   ../protocols/MSI_MOSI_inclusive-RnR-data.sm
	new file:   ../protocols/MSI_MOSI_inclusive-RnR.sm
	modified:   config/config.include
	modified:   config/rubyconfig.defaults
	modified:   generated/MSI_MOSI_inclusive-RnR/L2Cache_Controller.C
	modified:   generated/MSI_MOSI_inclusive-RnR/L2Cache_Transitions.C
	modified:   generated/MSI_MOSI_inclusive-RnR/default_param.h
	modified:   slicc_interface/RubySlicc_ComponentMapping.h
	modified:   system/CacheMemory.h
	modified:   ruby/system/CacheMemory.h
Modifications on L15 to make a PUTS when downgrade is received in L1_S state. Addition of L2_NRSS_IS state
Addition of the L2_NRSS_IS state
slicc included
L2_NRSS_IS <-- GETX, UPGRADEs
L1_SI <-- dg
L1 LRU_kid can be used now
L1 LRU_kid can be used now (rev 1)
L1 LRU_kid can be used now (rev 2)
L1 LRU_kid can be used now (rev 3)
Changes on Dram.C
RnR cache non-stalling + DRAM fixed
replacement comes from request networkgit add ../protocols/MSI_MOSI_inclusive-RnR-L2cache.sm  --> fixed
lifetrace + no requeue in DataRepl on SS, SO, MT
number of uses in L3 lines is now correctly accounted
lifetrace2
plenty of changes: DataArray can be a cache, lines with NRU bit are now requeued in FIFO organization