or into control thread's fp exceptions
can't execute frsr/fssr on ut
refactor disassembler, and add hwacha disassembler
more hwacha supervisor stuff
clean up SR_EA, the enable accelerator bit in status reg
implement vxcptsave/vxcptrestore
clarify vxcptsave/vxctkill semantics
Pass target machine's return code back to OS
include stdexcept
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprec
Implement "half-baked" half-precision instruction subset for Hwacha