i965/blorp: Add fields brw_blorp_mip_info::level,layer

The new fields define the 2D miptree slice to be used. A following commit
requires them in gen6_blorp_emit_depth_stencil_config.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP: Define struct intel_hiz_location
WIP/i965: Add intel_miptree_get_hiz_location

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP/i965: Refactor hiz state in brw_context::depthstencil
WIP/i965/blorp: Refactor with intel_hiz_location
WIP/intel: Refactor calculation of physical size of miptree level 0
WIP/intel: Allocate separate hiz bo for each mipslice
i965/blorp: Align rect prim for hiz ops

The hardware docs state that the rectangle primitive emitted during fast
depth clears and hiz resolves must be aligned to 8x4 pixels.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Enable hiz on Haswell

This patch sets the flag. That's all.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>