Add HDL parameters for HRES and BYTES_PER_PIXEL.
Merge branch 'master' into bryce_25mhz

Conflicts:
	ip/hdmi_out/pcores/hdmi_out_v1_00_a/hdl/verilog/user_logic.v
Set this branch's parameters to 640 HRES and 2 BYTES_PER_PIXEL (HDL doesn't use them yet).