ARM: dts: AM4372: Add DT for GP EVM

Add AM43x GP EVM minimal DT source, and adding common dtsi for
EPOS and GP EVMs so that common dt nodes should go in this file.
Also enabling RTC for GP evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ARM: dts: DRA7: Add DT node for DES IP

DRA7xx SoCs have a DES3DES IP. Add DT data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: dts: DRA7: Add DT node for AES IP

DRA7 SoC has same AES IP as on OMAP4. Add DT entries for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: OMAP4: hwmod: Add hwmod data for AES IP

Crypto modules AES0/1 belong to:
    PD_L4_PER power domain
    CD_L4_SEC clock domain
    On the L3, the AES modules are mapped to
    L3_CLK2: Peripherals and multimedia sub clock domain

We add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: OMAP4: hwmod: add hwmod data for DES IP

OMAP4 has a DES IP for DES and 3DES encryption, Add hwmod data for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: DRA7xx: hwmod: Add hwmod data for DES IP

dra7xx SoC has a DES module. Add the required data to hwmod.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: DRA7xx: hwmod: Add hwmod data for AES IP

DRA7xx SoC has same AES IP has OMAP4. Add hwmod data for PM functions
for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: dts: OMAP4: Add node for AES

OMAP4 has an AES module that uses the omap-aes crypto driver.
Add DT entries for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: dts: OMAP4: Add node for DES3DES module

OMAP4 has an DES3DES  module that uses the omap-des crypto driver.
Add DT entries for the same.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: configs: omap2plus: Enable crypto test module

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: OMAP: Disable POSTED mode for errata i103 and i767

Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx
(much like other OMAPs).  Reference discussions on forums [1] [2]. Earlier
patch solving this on other OMAPs [3].

For OMAP SoCs with this errata, the fix has been to not enable Posted mode.
However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode
is enabled on reset. So we not only need to ignore enabling of the POSTED bit
when the timer is requested, but also disable Posted mode if errata is present.

[1] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/285744.aspx
[2] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/270632.aspx
[3] http://www.spinics.net/lists/linux-omap/msg81770.html

Reported-by: Russ Dill <russ.dill@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
OMAP: hwmod: Add SYSC offsets for AES IP

The AES IP has the SIDLE offset by 2 and not 3, to allow SIDLE modes
to work for AES, we add a new SYSC type to HWMOD code.

Signed-off-by: Joel Fernandes <joelf@ti.com>
OMAP: DRA7: hwmod: Correct AES module SYSC type

Use the newly added sysc type4 for AES module.

Signed-off-by: Joel Fernandes <joelf@ti.com>
ARM: OMAP: Treat INTERFACE_IDLE also as an idle condition

For HW automatically transitioning clock domains, the IDLEST value goes to
INTERFACE IDLE. This is equivalent to the Fully idle state specially for
modules with fclk=iclk.

This prevents an error showing up previously during pm_runtime_put:
"_wait_target_disable failed"

The other (hackish way to fix this) is to disable HWSUP for the particular
clockdomain. These problems were seen and resolved on the AES IP on DRA7.

Signed-off-by: Joel Fernandes <joelf@ti.com>