Fix float64_to_uint64

The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken.  And this is, indeed, the case.

This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.

This contribution can be licensed under either the softfloat-2a or -2b
license.

V2: Added softfloat license statement.

V3: Modified to meet QEMU coding conventions.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Add float32_to_uint64()

This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.

This contribution can be licensed under either the softfloat-2a or -2b
license.

V2: Reduced patch to just this single routine per feedback from Peter
Maydell.

Signed-off-by: Tom Musta <tommusta@gmail.com>
target-arm: Add 64bit VFP floating and fixed-point conversion helpers

With AArch64 VFP can now handle 64bit wide VFP floating and fixed-point
conversions. Add handlers for them.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak. Split handlers into a round to zero variant and
 a round to current mode variant to ensure ARMv7 behaviour is correct.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point<->fixed-point" instructions

This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.

Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebased, updated to new infrastructure.
 Applied bug fixes from Michael Matz and Janne Grunau.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 fmov (scalar, immediate) instruction

This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 floating-point<->integer conversion instructions

Add support for the AArch64 floating-point<-> integer conversion
instructions to disas_fpintconv.

Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (1 source)"

This patch adds support for the "Floating-point data-processing (1 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merged single and double precision patches,
 updated to new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
softfloat: Remove unused argument from MINMAX macro.

The nan_exp argument is not used, so remove it.

Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1386158099-9239-4-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
softfloat: Add minNum() and maxNum() functions to softfloat.

Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.

Signed-off-by: Will Newton <will.newton@linaro.org>
Message-id: 1386158099-9239-5-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (2 source)"

This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merge single and double precision patches. Rebase
 and update to new infrastructure. Incorporate FMIN/FMAX support patch by
 Michael Matz.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Add AArch64 "Floating-point data-processing (3 source)"

This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, merged single and double precision patches.
 Implement using muladd as suggested by Richard Henderson.]
Signed-off-by: Will Newton <will.newton@linaro.org>
target-arm: Enable AArch64 floating point literal loads

Call do_fp_ld from handle_ld_lit to handle literal loads to floating
point registers.

Signed-off-by: Will Newton <will.newton@linaro.org>
linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext

Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.

Signed-off-by: Will Newton <will.newton@linaro.org>