rtl/cache: drop invalidate/flush all operations.

Just do invalidation/flushing with a line-by-line operation - this makes
it much easier to implement the valid/dirty memories with FPGA block
rams and can cut out on some extra state machines.

Software can trivially construct an invalidate all operation by looping
from 0 to the number of lines (from the cpuid registers) and
invalidating that line.