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ARM: OMAP4: L2X0: Update PL310 register bits

Memory tests have shown a memory corruption where updates to a
single cache line are lost, possibly due to ARM errata 732672:
An abort on the second part of a double linefill can cause
data corruption of the first part.  Workaround is to disable
double linefill.

Also instruction prefetch is disabled since it degrades the
the performance.

In addition changed prefetch offset default value to 0x05 in
the PL310 Prefetch Control Register to increase performance.

Based on K3.0 commits:
6f07d8f268 [Santosh Shilimkar <santosh.shilimkar@ti.com>]
e46d9adf9e [Colin Cross <ccross@android.com>]
3a0a7f5b86 [Santosh Shilimkar <santosh.shilimkar@ti.com>]

Change-Id: I9dd35d04417d9999466a086267b5c1ab17078229
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com>

Conflicts:
	arch/arm/include/asm/hardware/cache-l2x0.h
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