dvisampler: add core, EDID support
Instantiate DVI sampler core for both ports
software/bios: default length 4 for mr command
Use new ClockDomain API
MultiReg: remove idomain
dvisampler: add clocking and phase detector
dvisampler: fixes
dvisampler/datacapture: fix tap counter reg
dvisampler/datacapture: connect IODELAY IOCLK0
m1crg: set CLKIN_PERIOD for vga_clock_gen
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
dvisampler: use pix5x as IODELAY clock
dvisampler/clocking: proper pix5x reset synchronization