msm: socinfo: Add support for detecting Krait and Krait Pass
 2

Add APIs for checking whether the current CPU is Krait and
Krait Pass 2.

Change-Id: I5b28e8ae76b2df64675a6808092d792833931544
Signed-off-by: Jin Hong <jinh@codeaurora.org>
msm: socinfo: Add a cpu_is macro for msm8974

Add support for identifying the msm8974 SoC and update the
MIDR fallback table accordingly.

Change-Id: Idc34cac2963776b07ad59c0727bcb49ae42be1ea
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: socinfo: Add support for detecting Krait Pass 3

Add an API for checking whether the current CPU is Krait
Pass 3.

Change-Id: Id6893ded88ebd83c911720bf35a9a5c9a44fa128
Signed-off-by: Joel King <joelking@codeaurora.org>
msm: socinfo: add support for mpq8092

Add socinfo for mpq8092

Change-Id: I4e07e6a3482d9966e7e7e2bc7af37cfe9bd5a255
Signed-off-by: Ravi Kumar V <kumarrav@codeaurora.org>
msm: socinfo: add support for msm8226

Add dummy socinfo and support to get socinfo from bootloader for
msm8226

Change-Id: I245338a224a5c1917138259ce4874a4fcb212b5e
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
msm: cache_erp: Handle recoverable L1 errors

Some CPU designs may be able to recover from certain types
of L1 instruction cache errors. Rather than panicing
whenever any kind of L1 error is encountered, add an option
to selectively panic on recoverable L1 errors.

Change-Id: Id8beb0e58d41fa5319f4ca76c5f35e2162f8b704
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>