Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191940 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r191940 to see if it fixes the build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191941 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit to check e-mail address. Please discard this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191942 91177308-0d34-0410-b5e6-96231b3b80d8
Implement aarch64 neon instruction set AdvSIMD (3V elem).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
Restore LLVM_BUILD_RUNTIME option that was deleted in r191835, but is still used to control building of compiler-rt and libcxx

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191948 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Test commit to check e-mail address. Please discard this."

This reverts commit r191942.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191949 91177308-0d34-0410-b5e6-96231b3b80d8
Fix this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191958 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: preserve undef flag in pseudo instruction expanders

Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: do not add a regmask for TAILJUMPs

The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: optimizeSelect has to consider the previous register class

optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191963 91177308-0d34-0410-b5e6-96231b3b80d8
Fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191964 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191965 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191966 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily revert r191792 as it is causing some LTO debug failures
on platforms with relocations in debug info and also temporarily
revert r191800 due to conflicts with the revert of r191792.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191967 91177308-0d34-0410-b5e6-96231b3b80d8
Add lto_codegen_add_dso_symbol to the export list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191970 91177308-0d34-0410-b5e6-96231b3b80d8
lli: Check pipe creation for errors.

This is unlikely to ever fail, but ubuntu GCC warns when the return value is
unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191973 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily revert r176882 as it needs to be implemented in a different
way for all platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191975 91177308-0d34-0410-b5e6-96231b3b80d8
Fixing container/pointer bug in remote-lli found by ASan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191976 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: Sort inputs to commutative binary operations

Sort the operands of the other entries in the current vectorization root
according to the first entry's operands opcodes.

%conv0 = uitofp ...
%load0 = load float ...

= fmul %conv0, %load0
= fmul %load0, %conv1
= fmul %load0, %conv2

Make sure that we recursively vectorize <%conv0, %conv1, %conv2> and <%load0,
%load0, %load0>.

This makes it more likely to obtain vectorizable trees. We have to be careful
when we sort that we don't destroy 'good' existing ordering implied by source
order.

radar://15080067

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191977 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191978 91177308-0d34-0410-b5e6-96231b3b80d8