Another attempt at getting the XFAIL line right for this test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174588 91177308-0d34-0410-b5e6-96231b3b80d8
Remove this testcase until I can figure out how to properly conditionalize it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174591 91177308-0d34-0410-b5e6-96231b3b80d8
FDE::dumpHeader(): Forgot to fix one more formatting. It affected bigendian hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174602 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Fix assembly name for SETGT_INT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add tests for unsupported condition codes.

All of the le and lt variants are unsupported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174608 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for SET*_DX10 instructions

These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Consolidate sub register indices.

Use sub0-15 everywhere.

Patch by: Michel Dänzerr

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
FDE::dumpHeader(): Forgot to fix one more formatting, ... take two!

Excuse me, I could not test it locally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174614 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add pattern for flog2

22 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174615 91177308-0d34-0410-b5e6-96231b3b80d8
ARM cost model: Add costs for vector selects

Vector selects are cheap on NEON. They get lowered to a vbsl instruction.

radar://13158753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add basic support for more integer vector types.

v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Make sample intrinsic address parameter type overloaded.

Handle vectors of 1 to 16 integers.

Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174633 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Use proper instructions for array/shadow samplers.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174634 91177308-0d34-0410-b5e6-96231b3b80d8
[Object][ELF] Fix crash on no dynamic section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174639 91177308-0d34-0410-b5e6-96231b3b80d8
[Object][ELF] Add {begin,end}_elf_dynamic_symbols to non-virtually iterate over dynamic symbols.