Support mmxext (integer sse) subset on i386 (athlon).

Some processors like the AMD Athlon "Classic" support mmxext,
a sse1 subset. This subset is not properly detected by VEX.
The subset uses the same encoding as the sse1 instructions.

The subset is described at:
  http://support.amd.com/us/Embedded_TechDocs/22466.pdf
  https://en.wikipedia.org/wiki/3DNow!#3DNow.21_extensions

This introduces a new VEX_HWCAPS_X86_MMXEXT that sits between
the baseline (0) and VEX_HWCAPS_X86_SSE1. There is also a new
x86g_dirtyhelper_CPUID_mmxext to mimics a Athlon "Classic"
(Model 2, K75 "Pluto/Orion").

Groups all mmxext instructions together in one block.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2745 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add algebraic simplifications for Iop_And64 (same as for Iop_And32).
Remove isOnesU32 which is no longer needed.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2746 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add an optimisation for Iop_Left64.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2747 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Comment-only change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2748 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32/mips64: Fix the problem with lwl and lwr for mips32 and mips64.

This patch is fixing the problem with lwl and lwr for mips32 and mips64
that was discovered while running v8 tests for mips32.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2749 8f6e269a-dfd6-0310-a8e1-e2731360e62c
deltaIRExpr cannot handle Iex_VECRET and Iex_BBPTR and
needs to be guarded.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2750 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The current code is not properly handling a non-zero TH field in the
dcbt instruction, which is valid for several forms of data cache block
touch instructions.  This patch adds the needed support to
VEX/priv/guest_ppc_toIR.c.

Bugzilla 324518

git-svn-id: svn://svn.valgrind.org/vex/trunk@2751 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Update list of ignored files.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2752 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The patch used the binary constants 0b10000 and 0b10001.  The 0b designator
is supported by the GCC extensions but not all compilers seem to support the
0b extension in GCC.  Therefore, the binary constats were changed to their
equivalent hex values as suggested by Florian.

The Bugzilla for the change is 324518.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2753 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The existing overflow detection in VEX/priv/guest_ppc_toIR.c/set_XER_OV_64()
under the case PPCG_FLAG_OP_MULLW: does not apply to the mulldo as we need to
detect overflow when performing a Multiply Low Doubleword (not Multiply Low
Word). Hence, we added a new enumeration value PPCG_FLAG_OP_MULLD in
VEX/priv/guest_ppc_defs.h and a corresponding new case under which the
computation for detecting overflow for mulldo/mulldo. is added in
set_XER_OV_64(). The tests have been added to: none/tests/ppc32/jm-insns.c

Bugzilla 324594, submitted by Anmol P. Paralkar

Patch reviewed and tested by Carl Love


git-svn-id: svn://svn.valgrind.org/vex/trunk@2754 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add a few more optimisations for CmpwNEZ64, CmpNEZ32, and CmpNEZ64.
Observed on s390.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2755 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM
Power ISA 2.07. The first bugzilla in the series was: 322294: Add initial
support for IBM Power ISA 2.07

Phase 2 adds support for the following new instructions to
VEX/priv/guest_ppc_toIR.c:
 - lq, stq, lqarx, stqcx.
 - mfvsrwz, mtvsrwz
 - fmrgew, fmrgow

There is a corresponding test case for these instructions, see the bugzilla
for the commit number.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2756 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: fixed problem with Iop's for mips64.

Fixed problem with some Iop's that was discovered while running vbit-test
on mips64. Fixed operations are: Iop_1Uto64, Iop_Left64 and Iop_CmpwNEZ64.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2757 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Enhance ado_treebuild_BB to allow an expression preceding a Put
statement and containing one or more Get expressions to be
substituted in an expression following the Put statement.
That transformation is harmless as long as the guest state areas being
accessed by the Put and Get(s) do not overlap.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2758 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove dead code.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2759 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The Power ISA 2.07 document includes a correction to the description for the
behavior of the xscvspdp instruction, indicating that if the source argument
is a SNaN, it is first changed to a QNaN before being converted from
single-precision to double-precision. This updated information about the
xscvspdp instruction exposed a bug in the VEX implementation for that
instruction and also a bug in the testing for all instructions having
special behavior for single-precision SNaN arguments.

This patch fixes both the VEX bug in xscvspdp implementation:
The current implementation of xscvspdp emulates the instruction by
extracting the single-precision floating point from the vector register,
storing it in single-prcision, and then loading the data just stored using
the lfsx instruction. But the lfsx instruction does not change SNaN input
arguments to QNaN inputs before conversion to double-precision, so this
emulation is not sufficient for the xscvspdp instruction as described in the
current documentation. This patch fixes that issue by recognizing a SNaN input
and changing it to a QNaN before performing the emulation using lfsx.
While fixing the bug in xscvspdp implementation, it was also discovered that
xvcvspdp had the same issue where SNaN inputs were not being handled correctly,
so this patch also fixes its implementation, too

See bugzilla 324816.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2760 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Bug 323893 - SSE3 not available on amd cpus in valgrind.

Check minimum hardware capabilities, not exact matches to prevent
downgrading to baseline if the hardware has more capabilities than
we expect.

Note that this is still not exactly correct. CPUID should depend on
VEX capabilities, not on underlying CPU, see bug 324882.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2761 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: Add spechelper for s390_calculate_cc.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2762 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32: small cleanup in show_hwcaps_mips32

Small cleanup in show_hwcaps_mips32(). More will follow as we need to add
support for Cavium boards too.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2763 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: clean-up in hardware detection (Cavium/DSP ASEs)

This change is a clean up in MIPS hardware detection code.
New flag for Cavium Company ID is added, as well as the codes for 34K and
74K processors (MIPS Company ID). The later two represent platforms with DSP
ASEs implemented (Rev 1 and Rev 2 respectively). Macros to detect these two
platforms have been added as well.

Additional macros to extract Company ID out of hwcaps added as well, and
used where possible.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2764 8f6e269a-dfd6-0310-a8e1-e2731360e62c