cappuccino/execute_ctrl: omit reset logic to ctrl_rfb_o
cappuccino/ctrl: omit reset on spr_epcr

Value of spr_epcr is don't care until set explicitly anyways.
cappuccino/wb_mux: remove unused pc_i signal
cappuccino/wb_mux: omit reset for rf_result_o

Value is don't care until explicitly set.
cappuccino/wb_mux: remove !op_lsu_load_i restriction
cappuccino/decode_execute: omit reset on pc_execute_o
cappuccino/execute_ctrl: split ctrl_alu_result_o and ctrl_lsu_adr_o generation
cappuccino/fetch: omit reset of pc_decode

Value is don't care until explicitly set.
cappuccino/ctrl: change comment style to //
cappuccino/ctrl: remove enable signal on du_read_dat

The 'ack' signal will signal when data is valid,
so it's not needed to gate the data too.
execute_alu: move decoding of comp_op (op_setflag) to decode
Rename RAM modules

mor1kx_spram is actually a dual port ram, as it has seperate read and
write ports.
A common notion for such a dual port RAM is "simple dual port ram",
in contrast to the type of dual port ram that has two seperate read
and write ports that's commonly referred to as a "true dual port ram".
This updates the RAM modules to follow this notion.
execute_alu: move decoding of adder control signals to decode
execute_alu: move decoding of multiply ops to decode
execute_alu: move decoding of div ops to mor1kx_decode
execute_alu: move decoding of shift ops to mor1kx_decode
execute_alu: move decoding of ffl1 ops to mor1kx_decode
espresso/ctrl: simplify execute_valid generation
prontoespresso/ctrl: simplify execute_valid generation
cappuccino/decode_execute: reset op signals on pipeline_flush_i

Some of the op signals were missing the reset on pipeline_flush_i,
this fixes that.