AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
Fix style issues in AsmParser.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188798 91177308-0d34-0410-b5e6-96231b3b80d8
Marking MCJIT PIC tests as XFAIL on arm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188807 91177308-0d34-0410-b5e6-96231b3b80d8
Marking two more MCJIT PIC tests as XFAIL on i686

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Removing duplicate XFAIL markers

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Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188814 91177308-0d34-0410-b5e6-96231b3b80d8
Still more MCJIT PIC test XFAILs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188815 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Fix fast-isel copy/paste-o.

Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
Teach ConstantFolding about pointer address spaces

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188831 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: Fix invalid iterator errors

Update iterator when the SLP vectorizer changes the instructions in the basic
block by restarting the traversal of the basic block.

Patch by Yi Jiang!

Fixes PR 16899.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188832 91177308-0d34-0410-b5e6-96231b3b80d8
Fix include guards.


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[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
Use -disable-output and to suppress output and don't use a temporary file unless we need one.

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Add some constantness.


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[mips] Remove predicates that were incorrectly or unnecessarily added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add support for mfhc1 and mthc1.


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