fix corner case parallel instruction display

Instructions can be scheduled in parallel. Consecutive
parallel instructions are called a fetch packet.

If instruction n has it's parallel bit (p-bit) set, the
instruction n+1 is scheduled in parallel within the same
execute packet and is displayed with a leading '||'.
The last instruction of an execute packet is the one with
it's p-bit set to 0.

To correctly display the leading '||', it's necessary to
fetch the previous instruction in order to read the p-bit
value.

Execute packet can cross fetch packet boundary and if the
first instruction of a fetch packet scheduled in parallel
there exists 3 cases :

1/ Fetch packet 1 (FP1) is not header based (ie. all 32 bits
instructions :

FP1+20	:
FP1+24	|       FP1/word#6       |
FP1+28	|       FP1/word#7       |
	 ------------------------
FP2+0	|       FP2/word#0       |
	:

Instruction is displayed as parallel if bit 0 of 32 bits
FP1/word#7 is set.

2/ FP1 is header based and word #6 contains 2 16 bits
instructions.

FP1+20	:
FP1+24	| FP1/msb#6 | FP1/lsb#6  |
FP1+28	| <packet header/word#7> |
	 ------------------------
FP2+0	|       FP2/word#0       |
	:

Instruction is displayed as parallel if header's p-bit #13
is set (parallel bit of 16 bits instructions are stored in
the header).

3/ FP1 is header based and word #6 contains a single 32
bits instruction

FP1+20	:
FP1+24	|        FP1/word#6      |
FP1+28	| <packet header/word#7> |
	 ------------------------
FP2+0	|        FP2/word#0      |
	:

Instruction is displayed as parallel if bit 0 of 32 bits
word #6 is set.

Cases 1 & 2 were handled correctly while case 3 wasn't correctly
accounted for and defaulted to case 2, leading to missing or
incorrectly parallel instruction representation in output
disassembly. Split case 2/ in two 2/ and /3.
added testcase