Attempt to fix issue where screen would be garbled when there was a lot of write activity from CPU because of pixel FIFO underruns.
- Make SDRAM prioritize reads over writes.  The interconnect does prioritize reads from the VGA controller over the CPU, but it treats writes independently from reads. Since SDRAM previously prioritized writes, this meant the CPU could starve the VGA controller.
- Make VGA controller assert axi_arready a cycle earlier, checking if there is space available in the FIFO at the end of the read burst.