don't overwrite RSI on entry, RAX instead. would be better if we did't have to clobber any registers.
putting constants in a slightly saner place
add periodic timer to timing interface with an lapic implementation... which currently ignores the period specified
initial activations test, timer is only on BSP, but but control transfer works: Interrupt -> ISR -> dispatcher -> userspace thread scheduler -> executing thread.  timer interrupts during systemcalls will fall catashrophically
ignore all the things
whoops, forgot important file
somehow forgot to restore RSI upon return from an activation... breaking the thing that got interrupted
Pretty sure this disables interrupts during syscalls... hard to test
switch to page sized activation frames, with room for a stack and XOmBThread
make activations writable to userspace
instead of resuming activation immediately, convert activation to a thread and enqueue it.  call userspace interrupt handler (which re-enters the thread scheduler for now)
actually free activations
smaller (one instruction) race; rsp is also a 'spare' register
eliminates race condition, but IOPL should probably be fixed to prevent userspace from disabling interrupts
stuff userspace interrupt dispatch into arch.core.IDT and establish timer directly in kmain(). eliminates upstart kernel.core.dispatcher
generate IDT entries and handler stubs for 64 of 256 potential interrupts. dramatically increases kernel size, probably due to template bug
don't import mindrt.dstubs from libd, this makes dyndrt confused. instead just define abort next to exit, which it calls.
apps can now register local interrupt handlers, interrupt routing between apps doesn't exist yet
can initialize helper symbols at compile time
rewrite userspace interrupt dispatcher as stackless asm