Add in a write barrier after each if_arge write.

Without correct barriers, this code just plain doesn't work on the
mips74k cores (specifically the AR9344.)

In particular, the MDIO register accesses need this barriering or MII bus
access results in out-of-order garbage.

Tested:

* AR9344 (mips74k)
* AR9331 (mips24k)
Fix logic error.  MPPE only accepts protocol numbers 0x21 through 0xFA.

PR:	bin/175974
Add in the platform specific quirks to get the AR934x SoC ethernet
up and running.

* The MAC FIFO configurations needed updating;
* Reset the MDIO block at the same time the MAC block is reset;
* The default divisor needs changing as the DB120 runs at a higher
  base MDIO bus clock compared to other chips.

The long-term fix is to allow the system to have a target MDIO bus
clock rate and then calculate the most suitable divider to meet
that.  This will likely need implementing before stable external
PHY or switch support can be committed.

Tested:

* AR9344 (mips74k)
* AR9331 (mips24k)
Initial commit of AR9340 switch SoC support.

This is just the chip initialisation code (for now.)

It's not linked into the main build as it requires a bunch of other code
to be tidied up and committed.  But it indeed does function as advertised.

Tested:

* AR9344 SoC
Prepare to link in the AR934x SoC switch support.

* Add an AR9340 switch version entry;
* Support the switch being connected via MII;
* Add a flag to note that a switch is actually an internal
  switch rather than an external switch.

Now:

* The ar9340 switch can interconnect via MII;
* Since some slightly different phy/switch register access methods
  and quirks appear for the internal versus external switch,
  we will need a flag to mark it as an "internal" switch.

Tested:

* AR9344 (internal switch)
* AR9331 (internal switch)

TODO:

* Test the AR8316 switch!