common: improved RR arbiter

Conflicts:

	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd
genrams: removed dependency on Xilinx coregen, use native FIFO18/36 primitives on Virtex6

Conflicts:

	modules/genrams/xilinx/Manifest.py
	modules/genrams/xilinx/generic_dpram_sameclock.vhd
	modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd
genrams/generic_shiftreg_fifo: force native SRL implementation on Xilinx devices

Conflicts:

	modules/genrams/xilinx/Manifest.py
genrams/inferred_sync_fifo: fixed show ahead mode, keep output unchanged when rd_i = 0
wishbone/wb_xilinx_fpga_loader: testbench fixes
common: added gc_word_packer to manifest and package
common/gc_crc_gen: generic byte swapping

Conflicts:

	modules/common/gc_crc_gen.vhd
[xilinx] genrams/v6_hwfifo_wrapper: parameter/signal validation to avoid DRC errors
genrams/inferred_sync_fifo: assert full flag one cycle in advance
wishbone_pkg: added SDB descriptor for xwb_vic
common/gc_word_packer: uploaded missing source file
common/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart input and combinatorial output to reduce latency

Conflicts:

	modules/common/gc_crc_gen.vhd
wishbone/wb_vic: more verbose documentation
doc: initial (and incomplete) version of the manual
wishbone_pkg: added SDB desriptors for I2C, 1-ie and SPI masters
wishbone: added wb_simple_pwm PWM controller

Conflicts:

	modules/wishbone/Manifest.py
wishbone: updated wishbone package (PWM & new SDB descriptors), minor VHDL'93 compliance fix

Conflicts:

	modules/wishbone/wishbone_pkg.vhd
testbench/wishbone: TB for wb_simple_pwm
genrams/generic_shiftreg_fifo.vhd: reset pointer when reset is asserted
gc_extend_pulse: save some resources, don't need to use fixed size 32-bit counter