intermediate checkin
intermediate checkin
intermediate checkin
genxprojfrombsv runs to completion
remving busdefs
generated bsv is now complete.  I need to generate pragmas which reduce the number of scheduler warnings
fix errors/warnings in generated bsv
able to generate bitfiles for zedboard'
bsim now builds
bring memcpy HW into the new regime
memcpy bsim top
echo2proj android eecutable compiles
new implementation of directory as regfile
echo2 works in bsim