i915g: Stop calling draw_prepare_shader_outputs

It's not useful on i915g since we don't support primid. Fixes
piglit point tests on i915g.
i915g: Implement writemask fixup

The fixup code emulates non-BGRA render targets by adding an
extra instruction at the end of fragment shaders to swizzle the
output. To do this, we also swizzle the blend function. However
an oversight until now was that the writemask wasn't getting
swizzled. This patch fixes that which fixes a bunch of piglit
tests.
i965/gs: Don't assign gl_Layer its own slot in the VUE map.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965/vs: Move vs-specific code out of brw_vec4.h.

Now brw_vec4.h contains only code that is shared between the vertex
and geometry shaders.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vec4: Make with_writemask() non-static.

This will allow it to be shared between brw_vec4_visitor.cpp and
brw_vec4_vs_visitor.cpp (which will be created in the next patch).

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vs: Move vs-specific code out of brw_vec4_visitor.cpp.

This patch creates a new file brw_vec4_vs_visitor.cpp, to contain code
that is specific to the vertex shader.  Now the organization of vertex
shader and geometry shader visitor code is symmetric: vs-specific code
is in brw_vec4_vs_visitor.cpp, gs-specific code is in
brw_vec4_gs_visitor.cpp, and code shared between vs and gs is in
brw_vec4_visitor.cpp.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/gen7.5: Fix lower bound on number of VS URB entries.

Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.

At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader.  But when we turn on support for geometry
shaders, this lower limit will become important.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
nv30: fix inconsistent setting of push->user_priv

It's set to &nv30->bufctx everywhere else.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
glsl: propagate max_array_access through function calls

Fixes a bug where if an uniform array is passed to a function the accesses
to the array are not propagated so later all but the first vector of the
uniform array are removed in parcel_out_uniform_storage resulting in
broken shaders and out of bounds access to arrays in
brw::vec4_visitor::pack_uniform_registers.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-and-Tested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dominik Behr <dbehr@chromium.org>
i965: Remove never used RSR and RSL opcodes.

RSR and RSL are listed in the "Defeatured Instructions" section of the
965 PRM, Volume 4:

"The following instructions are removed from Gen4 implementation mainly
 due to implementation cost/schedule reasons.  They are candidates for
 future generations."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Remove never used DPA2 opcode.

DPA2 is listed in the "Defeatured Instructions" section of the
965 PRM, Volume 4:

"The following instructions are removed from Gen4 implementation mainly
 due to implementation cost/schedule reasons.  They are candidates for
 future generations."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
r600g/compute: Don't flush the cs in pipe_context::launch_grid()

This is the state tracker's responsibility.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
r600g/compute: Fix bug in compute memory pool

When adding a new buffer to the beginning of the memory pool, we were
accidentally deleting the buffer that was first in the buffer list.
This was caused by a bug in the memory pool's linked list
implementation.